!_TAG_FILE_FORMAT	2	/extended format; --format=1 will not append ;" to lines/
!_TAG_FILE_SORTED	1	/0=unsorted, 1=sorted, 2=foldcase/
!_TAG_PROGRAM_AUTHOR	Darren Hiebert	/dhiebert@users.sourceforge.net/
!_TAG_PROGRAM_NAME	Exuberant Ctags	//
!_TAG_PROGRAM_URL	http://ctags.sourceforge.net	/official site/
!_TAG_PROGRAM_VERSION	5.9~svn20110310	//
AIP200	ast_drv.h	/^	AIP200,$/;"	e	enum:ast_chip
AST1100	ast_drv.h	/^	AST1100,$/;"	e	enum:ast_chip
AST1180	ast_drv.h	/^	AST1180,$/;"	e	enum:ast_chip
AST2000	ast_drv.h	/^	AST2000,$/;"	e	enum:ast_chip
AST2100	ast_drv.h	/^	AST2100,$/;"	e	enum:ast_chip
AST2150	ast_drv.h	/^	AST2150,$/;"	e	enum:ast_chip
AST2200	ast_drv.h	/^	AST2200,$/;"	e	enum:ast_chip
AST2300	ast_drv.h	/^	AST2300,$/;"	e	enum:ast_chip
AST2400	ast_drv.h	/^	AST2400,$/;"	e	enum:ast_chip
AST2500	ast_drv.h	/^	AST2500,$/;"	e	enum:ast_chip
AST2500PreCatchCRT	ast_tables.h	50;"	d
AST2600	ast_drv.h	/^	AST2600,$/;"	e	enum:ast_chip
ASTDP_State	ast_drv.h	/^    u8 ASTDP_State;$/;"	m	struct:ast_private
AST_DDR2	ast_post.c	406;"	d	file:
AST_DDR3	ast_post.c	405;"	d	file:
AST_DEFAULT_HWC_NUM	ast_drv.h	96;"	d
AST_DRAM_1Gx16	ast_drv.h	82;"	d
AST_DRAM_1Gx32	ast_drv.h	84;"	d
AST_DRAM_2Gx16	ast_drv.h	85;"	d
AST_DRAM_4Gx16	ast_drv.h	86;"	d
AST_DRAM_512Mx16	ast_drv.h	81;"	d
AST_DRAM_512Mx32	ast_drv.h	83;"	d
AST_DRAM_8Gx16	ast_drv.h	87;"	d
AST_DRAM_TABLES_H	ast_dram_tables.h	3;"	d
AST_HWC_SIGNATURE_CHECKSUM	ast_drv.h	99;"	d
AST_HWC_SIGNATURE_HOTSPOTX	ast_drv.h	104;"	d
AST_HWC_SIGNATURE_HOTSPOTY	ast_drv.h	105;"	d
AST_HWC_SIGNATURE_SIZE	ast_drv.h	94;"	d
AST_HWC_SIGNATURE_SizeX	ast_drv.h	100;"	d
AST_HWC_SIGNATURE_SizeY	ast_drv.h	101;"	d
AST_HWC_SIGNATURE_X	ast_drv.h	102;"	d
AST_HWC_SIGNATURE_Y	ast_drv.h	103;"	d
AST_HWC_SIZE	ast_drv.h	93;"	d
AST_IO_AR_PORT_WRITE	ast_drv.h	154;"	d
AST_IO_CRTC_PORT	ast_drv.h	162;"	d
AST_IO_DAC_DATA	ast_drv.h	160;"	d
AST_IO_DAC_INDEX_READ	ast_drv.h	158;"	d
AST_IO_DAC_INDEX_WRITE	ast_drv.h	159;"	d
AST_IO_GR_PORT	ast_drv.h	161;"	d
AST_IO_INPUT_STATUS1_READ	ast_drv.h	163;"	d
AST_IO_MISC_PORT_READ	ast_drv.h	164;"	d
AST_IO_MISC_PORT_WRITE	ast_drv.h	155;"	d
AST_IO_MM_OFFSET	ast_drv.h	166;"	d
AST_IO_SEQ_PORT	ast_drv.h	157;"	d
AST_IO_VGA_ENABLE_PORT	ast_drv.h	156;"	d
AST_MAX_HWC_HEIGHT	ast_drv.h	91;"	d
AST_MAX_HWC_WIDTH	ast_drv.h	90;"	d
AST_MM_ALIGN_MASK	ast_drv.h	307;"	d
AST_MM_ALIGN_SHIFT	ast_drv.h	306;"	d
AST_TABLES_H	ast_tables.h	25;"	d
AST_TX_ASTDP	ast_drv.h	/^	AST_TX_ASTDP,$/;"	e	enum:ast_tx_chip
AST_TX_DP501	ast_drv.h	/^	AST_TX_DP501,$/;"	e	enum:ast_tx_chip
AST_TX_ITE66121	ast_drv.h	/^	AST_TX_ITE66121,$/;"	e	enum:ast_tx_chip
AST_TX_NONE	ast_drv.h	/^	AST_TX_NONE,$/;"	e	enum:ast_tx_chip
AST_TX_SIL164	ast_drv.h	/^	AST_TX_SIL164,$/;"	e	enum:ast_tx_chip
AST_VGA_DEVICE	ast_drv.c	51;"	d	file:
AST_VIDMEM_DEFAULT_SIZE	ast_drv.h	236;"	d
AST_VIDMEM_SIZE_128M	ast_drv.h	234;"	d
AST_VIDMEM_SIZE_16M	ast_drv.h	231;"	d
AST_VIDMEM_SIZE_32M	ast_drv.h	232;"	d
AST_VIDMEM_SIZE_64M	ast_drv.h	233;"	d
AST_VIDMEM_SIZE_8M	ast_drv.h	230;"	d
B_HDMITX_AUD_RST	ast_hdmitx.h	34;"	d
B_HDMITX_CSC_BYPASS	ast_hdmitx.h	237;"	d
B_HDMITX_CSC_RGB2YUV	ast_hdmitx.h	238;"	d
B_HDMITX_CSC_YUV2RGB	ast_hdmitx.h	239;"	d
B_HDMITX_VID_RST	ast_hdmitx.h	33;"	d
B_TXFFRST	ast_hdmitx.h	234;"	d
B_TXVIDSTABLE	ast_hdmitx.h	125;"	d
B_TX_2X656CLK	ast_hdmitx.h	225;"	d
B_TX_AFE_DRV_PWD	ast_hdmitx.h	216;"	d
B_TX_AFE_DRV_RST	ast_hdmitx.h	217;"	d
B_TX_AREF_RST	ast_hdmitx.h	32;"	d
B_TX_AUDCTS_MASK	ast_hdmitx.h	93;"	d
B_TX_AUDFMT_32BIT_I2S	ast_hdmitx.h	470;"	d
B_TX_AUDFMT_DELAY_1T_TO_WS	ast_hdmitx.h	473;"	d
B_TX_AUDFMT_FALL_EDGE_SAMPLE_WS	ast_hdmitx.h	480;"	d
B_TX_AUDFMT_LEFT_JUSTIFY	ast_hdmitx.h	471;"	d
B_TX_AUDFMT_LSB_SHIFT_FIRST	ast_hdmitx.h	478;"	d
B_TX_AUDFMT_MSB_SHIFT_FIRST	ast_hdmitx.h	477;"	d
B_TX_AUDFMT_NO_DELAY_TO_WS	ast_hdmitx.h	474;"	d
B_TX_AUDFMT_RIGHT_JUSTIFY	ast_hdmitx.h	472;"	d
B_TX_AUDFMT_RISE_EDGE_SAMPLE_WS	ast_hdmitx.h	479;"	d
B_TX_AUDFMT_STD_I2S	ast_hdmitx.h	469;"	d
B_TX_AUDFMT_WS0_LEFT	ast_hdmitx.h	475;"	d
B_TX_AUDFMT_WS0_RIGHT	ast_hdmitx.h	476;"	d
B_TX_AUDIO_OVFLW_MASK	ast_hdmitx.h	74;"	d
B_TX_AUD_EN_I2S0	ast_hdmitx.h	463;"	d
B_TX_AUD_EN_I2S1	ast_hdmitx.h	462;"	d
B_TX_AUD_EN_I2S2	ast_hdmitx.h	461;"	d
B_TX_AUD_EN_I2S3	ast_hdmitx.h	460;"	d
B_TX_AUD_EN_SPDIF	ast_hdmitx.h	464;"	d
B_TX_AUD_ERR2FLAT	ast_hdmitx.h	506;"	d
B_TX_AUD_FULLPKT	ast_hdmitx.h	467;"	d
B_TX_AUD_I2S	ast_hdmitx.h	459;"	d
B_TX_AUD_MULCH	ast_hdmitx.h	493;"	d
B_TX_AUD_S1VALID	ast_hdmitx.h	509;"	d
B_TX_AUD_S2VALID	ast_hdmitx.h	508;"	d
B_TX_AUD_S3VALID	ast_hdmitx.h	507;"	d
B_TX_AUD_SPDIF	ast_hdmitx.h	458;"	d
B_TX_AUD_SPXFLAT_SRC0	ast_hdmitx.h	505;"	d
B_TX_AUD_SPXFLAT_SRC1	ast_hdmitx.h	504;"	d
B_TX_AUD_SPXFLAT_SRC2	ast_hdmitx.h	503;"	d
B_TX_AUD_SPXFLAT_SRC3	ast_hdmitx.h	502;"	d
B_TX_AUTH_DONE_MASK	ast_hdmitx.h	88;"	d
B_TX_AUTH_FAIL_MASK	ast_hdmitx.h	89;"	d
B_TX_AUTO_OVER_SAMPLING_CLOCK	ast_hdmitx.h	187;"	d
B_TX_BANK0	ast_hdmitx.h	133;"	d
B_TX_BANK1	ast_hdmitx.h	134;"	d
B_TX_BLUE_SCR_MUTE	ast_hdmitx.h	300;"	d
B_TX_BURST_PKT	ast_hdmitx.h	551;"	d
B_TX_CD_24	ast_hdmitx.h	308;"	d
B_TX_CD_30	ast_hdmitx.h	309;"	d
B_TX_CD_36	ast_hdmitx.h	310;"	d
B_TX_CD_48	ast_hdmitx.h	311;"	d
B_TX_CD_NODEF	ast_hdmitx.h	307;"	d
B_TX_CHSTSEL	ast_hdmitx.h	495;"	d
B_TX_CLR_AUD_CTS	ast_hdmitx.h	129;"	d
B_TX_CLR_AUTH_DONE	ast_hdmitx.h	105;"	d
B_TX_CLR_AUTH_FAIL	ast_hdmitx.h	106;"	d
B_TX_CLR_AVMUTE	ast_hdmitx.h	297;"	d
B_TX_CLR_HDCP_SYNC_DET_FAIL	ast_hdmitx.h	117;"	d
B_TX_CLR_HPD	ast_hdmitx.h	108;"	d
B_TX_CLR_KSVLISTCHK	ast_hdmitx.h	104;"	d
B_TX_CLR_PKTACP	ast_hdmitx.h	101;"	d
B_TX_CLR_PKTAUD	ast_hdmitx.h	115;"	d
B_TX_CLR_PKTAVI	ast_hdmitx.h	116;"	d
B_TX_CLR_PKTGENERAL	ast_hdmitx.h	103;"	d
B_TX_CLR_PKTMPG	ast_hdmitx.h	113;"	d
B_TX_CLR_PKTNULL	ast_hdmitx.h	102;"	d
B_TX_CLR_PKTSPD	ast_hdmitx.h	114;"	d
B_TX_CLR_RXSENSE	ast_hdmitx.h	107;"	d
B_TX_CLR_VIDSTABLE	ast_hdmitx.h	112;"	d
B_TX_CLR_VID_UNSTABLE	ast_hdmitx.h	118;"	d
B_TX_CLR_VSYNC	ast_hdmitx.h	111;"	d
B_TX_COLOR_DEPTH_MASK	ast_hdmitx.h	306;"	d
B_TX_DDC_ACT	ast_hdmitx.h	158;"	d
B_TX_DDC_ARBILOSE	ast_hdmitx.h	161;"	d
B_TX_DDC_BUS_HANG_MASK	ast_hdmitx.h	77;"	d
B_TX_DDC_DONE	ast_hdmitx.h	157;"	d
B_TX_DDC_ERROR	ast_hdmitx.h	162;"	d
B_TX_DDC_FIFOEMPTY	ast_hdmitx.h	164;"	d
B_TX_DDC_FIFOFULL	ast_hdmitx.h	163;"	d
B_TX_DDC_FIFO_ERR_MASK	ast_hdmitx.h	76;"	d
B_TX_DDC_NOACK	ast_hdmitx.h	159;"	d
B_TX_DDC_NOACK_MASK	ast_hdmitx.h	75;"	d
B_TX_DDC_WAITBUS	ast_hdmitx.h	160;"	d
B_TX_DNFREE_GO	ast_hdmitx.h	243;"	d
B_TX_DSD	ast_hdmitx.h	513;"	d
B_TX_DVI_MODE	ast_hdmitx.h	294;"	d
B_TX_ENABLE_PKT	ast_hdmitx.h	562;"	d
B_TX_ENAVMUTERST	ast_hdmitx.h	233;"	d
B_TX_ENTEST	ast_hdmitx.h	30;"	d
B_TX_EN_DITHER	ast_hdmitx.h	241;"	d
B_TX_EN_TXCLK_COUNT	ast_hdmitx.h	204;"	d
B_TX_EN_UDFILTER	ast_hdmitx.h	242;"	d
B_TX_EN_ZERO_CTS	ast_hdmitx.h	494;"	d
B_TX_EXT_1024FS	ast_hdmitx.h	193;"	d
B_TX_EXT_128FS	ast_hdmitx.h	190;"	d
B_TX_EXT_256FS	ast_hdmitx.h	191;"	d
B_TX_EXT_512FS	ast_hdmitx.h	192;"	d
B_TX_HBR	ast_hdmitx.h	512;"	d
B_TX_HDCP_RST_HDMITX	ast_hdmitx.h	36;"	d
B_TX_HDCP_SYNC_DET_FAIL_MASK	ast_hdmitx.h	92;"	d
B_TX_HDMI_MODE	ast_hdmitx.h	293;"	d
B_TX_HDMI_RST	ast_hdmitx.h	35;"	d
B_TX_HPDETECT	ast_hdmitx.h	123;"	d
B_TX_HPD_MASK	ast_hdmitx.h	79;"	d
B_TX_INDDR	ast_hdmitx.h	223;"	d
B_TX_INTACTDONE	ast_hdmitx.h	130;"	d
B_TX_INTPOL_ACTH	ast_hdmitx.h	40;"	d
B_TX_INTPOL_ACTL	ast_hdmitx.h	39;"	d
B_TX_INT_ACTIVE	ast_hdmitx.h	122;"	d
B_TX_INT_AUD_CTS	ast_hdmitx.h	65;"	d
B_TX_INT_AUD_OVERFLOW	ast_hdmitx.h	45;"	d
B_TX_INT_AUTH_DONE	ast_hdmitx.h	61;"	d
B_TX_INT_AUTH_FAIL	ast_hdmitx.h	62;"	d
B_TX_INT_DDCFIFO_ERR	ast_hdmitx.h	48;"	d
B_TX_INT_DDC_BUS_HANG	ast_hdmitx.h	50;"	d
B_TX_INT_HDCP_SYNC_DET_FAIL	ast_hdmitx.h	55;"	d
B_TX_INT_HPD_PLUG	ast_hdmitx.h	52;"	d
B_TX_INT_KSVLIST_CHK	ast_hdmitx.h	60;"	d
B_TX_INT_OPENDRAIN	ast_hdmitx.h	42;"	d
B_TX_INT_PKTACP	ast_hdmitx.h	57;"	d
B_TX_INT_PKTAUD	ast_hdmitx.h	70;"	d
B_TX_INT_PKTAVI	ast_hdmitx.h	71;"	d
B_TX_INT_PKTGENERAL	ast_hdmitx.h	59;"	d
B_TX_INT_PKTMPG	ast_hdmitx.h	68;"	d
B_TX_INT_PKTNULL	ast_hdmitx.h	58;"	d
B_TX_INT_PKTSPD	ast_hdmitx.h	69;"	d
B_TX_INT_PUSHPULL	ast_hdmitx.h	41;"	d
B_TX_INT_RDDC_NOACK	ast_hdmitx.h	47;"	d
B_TX_INT_ROMACQ_BUS_HANG	ast_hdmitx.h	49;"	d
B_TX_INT_ROMACQ_NOACK	ast_hdmitx.h	46;"	d
B_TX_INT_RX_SENSE	ast_hdmitx.h	51;"	d
B_TX_INT_VIDSTABLE	ast_hdmitx.h	67;"	d
B_TX_INT_VID_UNSTABLE	ast_hdmitx.h	56;"	d
B_TX_INT_VSYNC	ast_hdmitx.h	66;"	d
B_TX_IN_RGB	ast_hdmitx.h	228;"	d
B_TX_IN_YUV422	ast_hdmitx.h	229;"	d
B_TX_IN_YUV444	ast_hdmitx.h	230;"	d
B_TX_IP_LOCK	ast_hdmitx.h	209;"	d
B_TX_KSVLISTCHK_MASK	ast_hdmitx.h	87;"	d
B_TX_MASTERDDC	ast_hdmitx.h	140;"	d
B_TX_MASTERHDCP	ast_hdmitx.h	142;"	d
B_TX_MASTERHOST	ast_hdmitx.h	141;"	d
B_TX_MASTERROM	ast_hdmitx.h	139;"	d
B_TX_MPG_FR	ast_hdmitx.h	655;"	d
B_TX_MPG_MF_B	ast_hdmitx.h	657;"	d
B_TX_MPG_MF_I	ast_hdmitx.h	656;"	d
B_TX_MPG_MF_MASK	ast_hdmitx.h	659;"	d
B_TX_MPG_MF_P	ast_hdmitx.h	658;"	d
B_TX_NODEF_PHASE	ast_hdmitx.h	301;"	d
B_TX_OSF_LOCK	ast_hdmitx.h	211;"	d
B_TX_PCLKDIV2	ast_hdmitx.h	226;"	d
B_TX_PHASE_RESYNC	ast_hdmitx.h	302;"	d
B_TX_PKT_ACP_MASK	ast_hdmitx.h	84;"	d
B_TX_PKT_AUD_MASK	ast_hdmitx.h	98;"	d
B_TX_PKT_AVI_MASK	ast_hdmitx.h	82;"	d
B_TX_PKT_GEN_MASK	ast_hdmitx.h	86;"	d
B_TX_PKT_MPG_MASK	ast_hdmitx.h	96;"	d
B_TX_PKT_NULL_MASK	ast_hdmitx.h	85;"	d
B_TX_PKT_SPD_MASK	ast_hdmitx.h	97;"	d
B_TX_PKT_VID_UNSTABLE_MASK	ast_hdmitx.h	83;"	d
B_TX_REF_RST_HDMITX	ast_hdmitx.h	31;"	d
B_TX_REPEAT_PKT	ast_hdmitx.h	563;"	d
B_TX_ROM_ACTIVE	ast_hdmitx.h	173;"	d
B_TX_ROM_ARBILOSE	ast_hdmitx.h	176;"	d
B_TX_ROM_BUSHANG	ast_hdmitx.h	177;"	d
B_TX_ROM_DONE	ast_hdmitx.h	172;"	d
B_TX_ROM_NOACK	ast_hdmitx.h	174;"	d
B_TX_ROM_WAITBUS	ast_hdmitx.h	175;"	d
B_TX_RXSENDETECT	ast_hdmitx.h	124;"	d
B_TX_RXSEN_MASK	ast_hdmitx.h	78;"	d
B_TX_S0RLCHG	ast_hdmitx.h	499;"	d
B_TX_S1RLCHG	ast_hdmitx.h	498;"	d
B_TX_S2RLCHG	ast_hdmitx.h	497;"	d
B_TX_S3RLCHG	ast_hdmitx.h	496;"	d
B_TX_SELSRC0	ast_hdmitx.h	490;"	d
B_TX_SELSRC1	ast_hdmitx.h	489;"	d
B_TX_SELSRC2	ast_hdmitx.h	488;"	d
B_TX_SELSRC3	ast_hdmitx.h	487;"	d
B_TX_SETAVMUTE	ast_hdmitx.h	299;"	d
B_TX_SET_AVMUTE	ast_hdmitx.h	298;"	d
B_TX_SINGLE_PKT	ast_hdmitx.h	550;"	d
B_TX_SPDIFTC	ast_hdmitx.h	456;"	d
B_TX_START_CIPHER_GEN	ast_hdmitx.h	181;"	d
B_TX_STOP_CIPHER_GEN	ast_hdmitx.h	182;"	d
B_TX_SW_CTS	ast_hdmitx.h	552;"	d
B_TX_SYNCEMB	ast_hdmitx.h	224;"	d
B_TX_VDO_LATCH_EDGE	ast_hdmitx.h	205;"	d
B_TX_VIDSTABLE_MASK	ast_hdmitx.h	95;"	d
B_TX_VSYNC_MASK	ast_hdmitx.h	94;"	d
B_TX_XP_LOCK	ast_hdmitx.h	210;"	d
CBR_PASSNUM	ast_post.c	439;"	d	file:
CBR_PASSNUM2	ast_post.c	440;"	d	file:
CBR_PASSNUM_AST2150	ast_post.c	146;"	d	file:
CBR_PATNUM	ast_post.c	444;"	d	file:
CBR_PATNUM_AST2150	ast_post.c	151;"	d	file:
CBR_SIZE0	ast_post.c	436;"	d	file:
CBR_SIZE1	ast_post.c	437;"	d	file:
CBR_SIZE2	ast_post.c	438;"	d	file:
CBR_SIZE_AST2150	ast_post.c	145;"	d	file:
CBR_THRESHOLD	ast_post.c	441;"	d	file:
CBR_THRESHOLD2	ast_post.c	442;"	d	file:
CBR_THRESHOLD2_AST2150	ast_post.c	148;"	d	file:
CBR_THRESHOLD_AST2150	ast_post.c	147;"	d	file:
CEA_1280x720p50	ast_hdmitx.h	/^    CEA_1280x720p50,$/;"	e	enum:_mode_id
CEA_1280x720p60	ast_hdmitx.h	/^    CEA_1280x720p60,$/;"	e	enum:_mode_id
CEA_1440x240p60	ast_hdmitx.h	/^    CEA_1440x240p60,$/;"	e	enum:_mode_id
CEA_1440x288p50	ast_hdmitx.h	/^    CEA_1440x288p50,$/;"	e	enum:_mode_id
CEA_1440x480i60	ast_hdmitx.h	/^    CEA_1440x480i60,$/;"	e	enum:_mode_id
CEA_1440x480p60	ast_hdmitx.h	/^    CEA_1440x480p60,$/;"	e	enum:_mode_id
CEA_1440x576i50	ast_hdmitx.h	/^    CEA_1440x576i50,$/;"	e	enum:_mode_id
CEA_1440x576p50	ast_hdmitx.h	/^    CEA_1440x576p50,$/;"	e	enum:_mode_id
CEA_1920x1080i50	ast_hdmitx.h	/^    CEA_1920x1080i50,$/;"	e	enum:_mode_id
CEA_1920x1080i60	ast_hdmitx.h	/^    CEA_1920x1080i60,$/;"	e	enum:_mode_id
CEA_1920x1080p24	ast_hdmitx.h	/^    CEA_1920x1080p24,$/;"	e	enum:_mode_id
CEA_1920x1080p25	ast_hdmitx.h	/^    CEA_1920x1080p25,$/;"	e	enum:_mode_id
CEA_1920x1080p30	ast_hdmitx.h	/^    CEA_1920x1080p30,$/;"	e	enum:_mode_id
CEA_1920x1080p50	ast_hdmitx.h	/^    CEA_1920x1080p50,$/;"	e	enum:_mode_id
CEA_1920x1080p60	ast_hdmitx.h	/^    CEA_1920x1080p60,$/;"	e	enum:_mode_id
CEA_2880x240p60	ast_hdmitx.h	/^    CEA_2880x240p60,$/;"	e	enum:_mode_id
CEA_2880x288p50	ast_hdmitx.h	/^    CEA_2880x288p50,$/;"	e	enum:_mode_id
CEA_2880x480i60	ast_hdmitx.h	/^    CEA_2880x480i60,$/;"	e	enum:_mode_id
CEA_2880x576i50	ast_hdmitx.h	/^    CEA_2880x576i50,$/;"	e	enum:_mode_id
CEA_640x480p60	ast_hdmitx.h	/^    CEA_640x480p60,$/;"	e	enum:_mode_id
CEA_720x240p60	ast_hdmitx.h	/^    CEA_720x240p60,$/;"	e	enum:_mode_id
CEA_720x288p50	ast_hdmitx.h	/^    CEA_720x288p50,$/;"	e	enum:_mode_id
CEA_720x480i60	ast_hdmitx.h	/^    CEA_720x480i60,$/;"	e	enum:_mode_id
CEA_720x480p60	ast_hdmitx.h	/^    CEA_720x480p60,$/;"	e	enum:_mode_id
CEA_720x576i50	ast_hdmitx.h	/^    CEA_720x576i50,$/;"	e	enum:_mode_id
CEA_720x576p50	ast_hdmitx.h	/^    CEA_720x576p50,$/;"	e	enum:_mode_id
CEC_I2C_SLAVE_ADDR	ast_hdmitx.h	14;"	d
CMD_DDC_ABORT	ast_hdmitx.h	154;"	d
CMD_DDC_SEQ_BURSTREAD	ast_hdmitx.h	149;"	d
CMD_EDID_READ	ast_hdmitx.h	151;"	d
CMD_FIFO_CLR	ast_hdmitx.h	152;"	d
CMD_GEN_SCLCLK	ast_hdmitx.h	153;"	d
CMD_LINK_CHKREAD	ast_hdmitx.h	150;"	d
Charx8Dot	ast_tables.h	34;"	d
ClearDDCFIFO_HDMITX_Table	ast_hdmitx.c	/^RegSetEntry ClearDDCFIFO_HDMITX_Table[] = {$/;"	v
DDC_EDID_ADDRESS	ast_hdmitx.h	6;"	d
DDC_FIFO_MAXREQ	ast_hdmitx.h	7;"	d
DDC_HDCP_ADDRESS	ast_hdmitx.h	5;"	d
DPControlPower	ast_drv.h	329;"	d
DRIVER_AUTHOR	ast_drv.c	/^MODULE_AUTHOR(DRIVER_AUTHOR);$/;"	v
DRIVER_AUTHOR	ast_drv.h	43;"	d
DRIVER_DATE	ast_drv.h	47;"	d
DRIVER_DESC	ast_drv.c	/^MODULE_DESCRIPTION(DRIVER_DESC);$/;"	v
DRIVER_DESC	ast_drv.h	46;"	d
DRIVER_MAJOR	ast_drv.h	49;"	d
DRIVER_MINOR	ast_drv.h	50;"	d
DRIVER_NAME	ast_drv.h	45;"	d
DRIVER_PATCHLEVEL	ast_drv.h	51;"	d
DoubleScanMode	ast_tables.h	36;"	d
EGAModeIndex	ast_tables.h	29;"	d
Frame_Pcaking	ast_hdmitx.h	666;"	d
GetI2CReg	ast_hdmitx.c	/^static u8 GetI2CReg(struct drm_device *dev, u8 jChannel, u8 DeviceAddr, u8 jIndex)$/;"	f	file:
HBorder	ast_tables.h	38;"	d
HDMITXDEV	ast_hdmitx.h	/^} HDMITXDEV ;$/;"	t	typeref:struct:_HDMITXDEV_STRUCT
HDMITX_AUD_I2S_2ch_24bit	ast_hdmitx.c	/^RegSetEntry HDMITX_AUD_I2S_2ch_24bit[] =$/;"	v
HDMITX_AUD_SPDIF_2ch_24bit	ast_hdmitx.c	/^RegSetEntry HDMITX_AUD_SPDIF_2ch_24bit[] =$/;"	v
HDMITX_AndReg_Byte	ast_hdmitx.h	322;"	d
HDMITX_Aud_CHStatus_LPCM_20bit_48Khz	ast_hdmitx.c	/^RegSetEntry HDMITX_Aud_CHStatus_LPCM_20bit_48Khz[] =$/;"	v
HDMITX_DeaultAudioInfo_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_DeaultAudioInfo_Table[] = {$/;"	v
HDMITX_DefaultAVIInfo_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_DefaultAVIInfo_Table[] = {$/;"	v
HDMITX_DefaultAudio_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_DefaultAudio_Table[] = {$/;"	v
HDMITX_DefaultVideo_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_DefaultVideo_Table[] = {$/;"	v
HDMITX_DisableVideoOutput_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_DisableVideoOutput_Table[] = {$/;"	v
HDMITX_Init_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_Init_Table[] = {$/;"	v
HDMITX_OrReg_Byte	ast_hdmitx.h	321;"	d
HDMITX_PwrDown_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_PwrDown_Table[] = {$/;"	v
HDMITX_PwrOn_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_PwrOn_Table[] = {$/;"	v
HDMITX_ReadI2C_Byte	ast_hdmitx.c	/^static u8 HDMITX_ReadI2C_Byte(struct drm_device *dev, u8 RegAddr)$/;"	f	file:
HDMITX_ReadI2C_ByteN	ast_hdmitx.c	/^static bool HDMITX_ReadI2C_ByteN(struct drm_device *dev, u8 RegAddr,u8 *pData,int N)$/;"	f	file:
HDMITX_SetDVI_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_SetDVI_Table[] = {$/;"	v
HDMITX_SetHDMI_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_SetHDMI_Table[] = {$/;"	v
HDMITX_SetI2C_Byte	ast_hdmitx.c	/^static bool HDMITX_SetI2C_Byte(struct drm_device *dev, u8 Reg,u8 Mask,u8 Value)$/;"	f	file:
HDMITX_SetOutput_Table	ast_hdmitx.c	/^RegSetEntry HDMITX_SetOutput_Table [] = {$/;"	v
HDMITX_WriteI2C_Byte	ast_hdmitx.c	/^static bool HDMITX_WriteI2C_Byte(struct drm_device *dev, u8 RegAddr,u8 Data)$/;"	f	file:
HDMI_I2C_CHANNEL	ast_hdmitx.h	12;"	d
HDMI_TX_I2C_SLAVE_ADDR	ast_hdmitx.h	13;"	d
HalfDCLK	ast_tables.h	35;"	d
HiCModeIndex	ast_tables.h	31;"	d
I2C_ADDR	ast_hdmitx.h	/^	u8 I2C_ADDR ;$/;"	m	struct:_HDMITXDEV_STRUCT
I2C_BASE	ast_hdmitx.c	7;"	d	file:
I2C_DEV	ast_hdmitx.h	/^	u8 I2C_DEV ;$/;"	m	struct:_HDMITXDEV_STRUCT
I2C_Read_Byte	ast_hdmitx.c	/^static u8 I2C_Read_Byte(struct drm_device *dev, u8 Addr,u8 RegAddr)$/;"	f	file:
I2C_Read_ByteN	ast_hdmitx.c	/^static bool I2C_Read_ByteN(struct drm_device *dev, u8 Addr, u8 RegAddr, u8 *pData, int N)$/;"	f	file:
I2C_Write_Byte	ast_hdmitx.c	/^static bool I2C_Write_Byte(struct drm_device *dev, u8 Addr,u8 RegAddr,u8 Data)$/;"	f	file:
I2C_Write_ByteN	ast_hdmitx.c	/^static bool I2C_Write_ByteN(struct drm_device *dev, u8 Addr,u8 RegAddr,u8 *pData,int N)$/;"	f	file:
INCLUDE_VERMAGIC	ast.mod.c	2;"	d	file:
INIT_CLK_HIGH	ast_hdmitx.c	256;"	d	file:
InvAudCLK	ast_hdmitx.c	251;"	d	file:
InvAudCLK	ast_hdmitx.c	253;"	d	file:
KERNELDIR	Makefile	/^    	KERNELDIR ?= \/lib\/modules\/$(shell uname -r)\/build$/;"	m
LineCompareOff	ast_tables.h	37;"	d
MODE_ID	ast_hdmitx.h	/^} MODE_ID ;$/;"	t	typeref:enum:_mode_id
M_TX_AUD_16BIT	ast_hdmitx.h	451;"	d
M_TX_AUD_18BIT	ast_hdmitx.h	452;"	d
M_TX_AUD_20BIT	ast_hdmitx.h	453;"	d
M_TX_AUD_24BIT	ast_hdmitx.h	454;"	d
M_TX_AUD_SWL	ast_hdmitx.h	450;"	d
M_TX_COLOR_DEPTH	ast_hdmitx.h	305;"	d
M_TX_CSC_SEL	ast_hdmitx.h	240;"	d
M_TX_CTSINTSTEP	ast_hdmitx.h	128;"	d
M_TX_DEVID	ast_hdmitx.h	25;"	d
M_TX_EXT_MCLK_SEL	ast_hdmitx.h	189;"	d
M_TX_INCLKDLY	ast_hdmitx.h	222;"	d
M_TX_INCOLMOD	ast_hdmitx.h	227;"	d
M_TX_OSCLK_SEL	ast_hdmitx.h	186;"	d
M_TX_REVID	ast_hdmitx.h	27;"	d
NHSync	ast_tables.h	42;"	d
NVSync	ast_tables.h	44;"	d
NewModeInfo	ast_tables.h	41;"	d
O_TX_COLOR_DEPTH	ast_hdmitx.h	304;"	d
O_TX_CTSINTSTEP	ast_hdmitx.h	127;"	d
O_TX_DEVID	ast_hdmitx.h	24;"	d
O_TX_EXT_MCLK_SEL	ast_hdmitx.h	188;"	d
O_TX_FIFO0SEL	ast_hdmitx.h	486;"	d
O_TX_FIFO1SEL	ast_hdmitx.h	485;"	d
O_TX_FIFO2SEL	ast_hdmitx.h	484;"	d
O_TX_FIFO3SEL	ast_hdmitx.h	483;"	d
O_TX_INCLKDLY	ast_hdmitx.h	221;"	d
O_TX_OSCLK_SEL	ast_hdmitx.h	185;"	d
O_TX_REVID	ast_hdmitx.h	26;"	d
OrMask	ast_hdmitx.h	/^    u8 OrMask ;$/;"	m	struct:structRegSetEntry
PCI_CHIP_AIP200	ast_drv.h	56;"	d
PCI_CHIP_AST1180	ast_drv.h	55;"	d
PCI_CHIP_AST2000	ast_drv.h	53;"	d
PCI_CHIP_AST2100	ast_drv.h	54;"	d
PCI_VENDOR_ASPEED	ast_drv.c	47;"	d	file:
PCLKINV	ast_hdmitx.c	245;"	d	file:
PCLKINV	ast_hdmitx.c	247;"	d	file:
PCLK_HIGH	ast_hdmitx.h	/^    PCLK_HIGH$/;"	e	enum:__anon3
PCLK_LOW	ast_hdmitx.h	/^    PCLK_LOW = 0 ,$/;"	e	enum:__anon3
PCLK_MEDIUM	ast_hdmitx.h	/^    PCLK_MEDIUM,$/;"	e	enum:__anon3
PHSync	ast_tables.h	43;"	d
PVSync	ast_tables.h	45;"	d
PWD	Makefile	/^    PWD := $(shell pwd)$/;"	m
RCLK	ast_hdmitx.h	/^        unsigned long RCLK ;$/;"	m	struct:_HDMITXDEV_STRUCT
REGIDX_010	ast_dram_tables.h	149;"	d
REGIDX_014	ast_dram_tables.h	150;"	d
REGIDX_018	ast_dram_tables.h	151;"	d
REGIDX_020	ast_dram_tables.h	152;"	d
REGIDX_024	ast_dram_tables.h	153;"	d
REGIDX_02C	ast_dram_tables.h	154;"	d
REGIDX_030	ast_dram_tables.h	155;"	d
REGIDX_214	ast_dram_tables.h	156;"	d
REGIDX_2E0	ast_dram_tables.h	157;"	d
REGIDX_2E4	ast_dram_tables.h	158;"	d
REGIDX_2E8	ast_dram_tables.h	159;"	d
REGIDX_2EC	ast_dram_tables.h	160;"	d
REGIDX_2F0	ast_dram_tables.h	161;"	d
REGIDX_2F4	ast_dram_tables.h	162;"	d
REGIDX_2F8	ast_dram_tables.h	163;"	d
REGIDX_PLL	ast_dram_tables.h	165;"	d
REGIDX_RFC	ast_dram_tables.h	164;"	d
REGPktAudCTS0	ast_hdmitx.h	519;"	d
REGPktAudCTS1	ast_hdmitx.h	520;"	d
REGPktAudCTS2	ast_hdmitx.h	521;"	d
REGPktAudCTSCnt0	ast_hdmitx.h	525;"	d
REGPktAudCTSCnt1	ast_hdmitx.h	526;"	d
REGPktAudCTSCnt2	ast_hdmitx.h	527;"	d
REGPktAudN0	ast_hdmitx.h	522;"	d
REGPktAudN1	ast_hdmitx.h	523;"	d
REGPktAudN2	ast_hdmitx.h	524;"	d
REGTBL_NUM	ast_dram_tables.h	148;"	d
REG_TX_3D_INFO_CTRL	ast_hdmitx.h	565;"	d
REG_TX_ACP_CTRL	ast_hdmitx.h	555;"	d
REG_TX_AFE_DRV_CTRL	ast_hdmitx.h	214;"	d
REG_TX_AKSV_RD_BYTE5	ast_hdmitx.h	200;"	d
REG_TX_AN_GENERATE	ast_hdmitx.h	180;"	d
REG_TX_AUD0CHST_CHTNUM	ast_hdmitx.h	536;"	d
REG_TX_AUD1CHST_CHTNUM	ast_hdmitx.h	538;"	d
REG_TX_AUD2CHST_CHTNUM	ast_hdmitx.h	540;"	d
REG_TX_AUD3CHST_CHTNUM	ast_hdmitx.h	542;"	d
REG_TX_AUDCHST_CAT	ast_hdmitx.h	534;"	d
REG_TX_AUDCHST_CA_FS	ast_hdmitx.h	544;"	d
REG_TX_AUDCHST_MODE	ast_hdmitx.h	530;"	d
REG_TX_AUDCHST_OFS_WL	ast_hdmitx.h	546;"	d
REG_TX_AUDCHST_SRCNUM	ast_hdmitx.h	535;"	d
REG_TX_AUDIO_CTRL0	ast_hdmitx.h	449;"	d
REG_TX_AUDIO_CTRL1	ast_hdmitx.h	466;"	d
REG_TX_AUDIO_CTRL3	ast_hdmitx.h	492;"	d
REG_TX_AUDIO_FIFOMAP	ast_hdmitx.h	482;"	d
REG_TX_AUD_COUNT	ast_hdmitx.h	213;"	d
REG_TX_AUD_HDAUDIO	ast_hdmitx.h	511;"	d
REG_TX_AUD_INFOFRM_CTRL	ast_hdmitx.h	559;"	d
REG_TX_AUD_SRCVALID_FLAT	ast_hdmitx.h	501;"	d
REG_TX_AVIINFO_DB1	ast_hdmitx.h	604;"	d
REG_TX_AVIINFO_DB10	ast_hdmitx.h	613;"	d
REG_TX_AVIINFO_DB11	ast_hdmitx.h	614;"	d
REG_TX_AVIINFO_DB12	ast_hdmitx.h	615;"	d
REG_TX_AVIINFO_DB13	ast_hdmitx.h	616;"	d
REG_TX_AVIINFO_DB2	ast_hdmitx.h	605;"	d
REG_TX_AVIINFO_DB3	ast_hdmitx.h	606;"	d
REG_TX_AVIINFO_DB4	ast_hdmitx.h	607;"	d
REG_TX_AVIINFO_DB5	ast_hdmitx.h	608;"	d
REG_TX_AVIINFO_DB6	ast_hdmitx.h	609;"	d
REG_TX_AVIINFO_DB7	ast_hdmitx.h	610;"	d
REG_TX_AVIINFO_DB8	ast_hdmitx.h	611;"	d
REG_TX_AVIINFO_DB9	ast_hdmitx.h	612;"	d
REG_TX_AVIINFO_SUM	ast_hdmitx.h	617;"	d
REG_TX_AVI_INFOFRM_CTRL	ast_hdmitx.h	558;"	d
REG_TX_AV_MUTE	ast_hdmitx.h	295;"	d
REG_TX_BANK_CTRL	ast_hdmitx.h	132;"	d
REG_TX_BUSHOLD_T	ast_hdmitx.h	170;"	d
REG_TX_CLK_CTRL0	ast_hdmitx.h	184;"	d
REG_TX_CLK_CTRL1	ast_hdmitx.h	203;"	d
REG_TX_CLK_STATUS1	ast_hdmitx.h	207;"	d
REG_TX_CLK_STATUS2	ast_hdmitx.h	208;"	d
REG_TX_CSC_COFF	ast_hdmitx.h	251;"	d
REG_TX_CSC_CTRL	ast_hdmitx.h	236;"	d
REG_TX_CSC_GAIN1V_H	ast_hdmitx.h	274;"	d
REG_TX_CSC_GAIN1V_L	ast_hdmitx.h	273;"	d
REG_TX_CSC_GAIN2V_H	ast_hdmitx.h	276;"	d
REG_TX_CSC_GAIN2V_L	ast_hdmitx.h	275;"	d
REG_TX_CSC_GAIN3V_H	ast_hdmitx.h	278;"	d
REG_TX_CSC_GAIN3V_L	ast_hdmitx.h	277;"	d
REG_TX_CSC_MTX11_H	ast_hdmitx.h	255;"	d
REG_TX_CSC_MTX11_L	ast_hdmitx.h	254;"	d
REG_TX_CSC_MTX12_H	ast_hdmitx.h	257;"	d
REG_TX_CSC_MTX12_L	ast_hdmitx.h	256;"	d
REG_TX_CSC_MTX13_H	ast_hdmitx.h	259;"	d
REG_TX_CSC_MTX13_L	ast_hdmitx.h	258;"	d
REG_TX_CSC_MTX21_H	ast_hdmitx.h	261;"	d
REG_TX_CSC_MTX21_L	ast_hdmitx.h	260;"	d
REG_TX_CSC_MTX22_H	ast_hdmitx.h	263;"	d
REG_TX_CSC_MTX22_L	ast_hdmitx.h	262;"	d
REG_TX_CSC_MTX23_H	ast_hdmitx.h	265;"	d
REG_TX_CSC_MTX23_L	ast_hdmitx.h	264;"	d
REG_TX_CSC_MTX31_H	ast_hdmitx.h	267;"	d
REG_TX_CSC_MTX31_L	ast_hdmitx.h	266;"	d
REG_TX_CSC_MTX32_H	ast_hdmitx.h	269;"	d
REG_TX_CSC_MTX32_L	ast_hdmitx.h	268;"	d
REG_TX_CSC_MTX33_H	ast_hdmitx.h	271;"	d
REG_TX_CSC_MTX33_L	ast_hdmitx.h	270;"	d
REG_TX_CSC_RGBOFF	ast_hdmitx.h	252;"	d
REG_TX_CSC_YOFF	ast_hdmitx.h	250;"	d
REG_TX_DDC_CMD	ast_hdmitx.h	148;"	d
REG_TX_DDC_EDIDSEG	ast_hdmitx.h	147;"	d
REG_TX_DDC_HEADER	ast_hdmitx.h	144;"	d
REG_TX_DDC_MASTER_CTRL	ast_hdmitx.h	138;"	d
REG_TX_DDC_READFIFO	ast_hdmitx.h	166;"	d
REG_TX_DDC_REQCOUNT	ast_hdmitx.h	146;"	d
REG_TX_DDC_REQOFF	ast_hdmitx.h	145;"	d
REG_TX_DDC_STATUS	ast_hdmitx.h	156;"	d
REG_TX_DEVICE_ID0	ast_hdmitx.h	21;"	d
REG_TX_DEVICE_ID1	ast_hdmitx.h	22;"	d
REG_TX_GCP	ast_hdmitx.h	296;"	d
REG_TX_HDCP_HEADER	ast_hdmitx.h	168;"	d
REG_TX_HDMI_MODE	ast_hdmitx.h	292;"	d
REG_TX_HSEL	ast_hdmitx.h	283;"	d
REG_TX_HSH	ast_hdmitx.h	284;"	d
REG_TX_HSSL	ast_hdmitx.h	282;"	d
REG_TX_HVPol	ast_hdmitx.h	280;"	d
REG_TX_HfPixel	ast_hdmitx.h	281;"	d
REG_TX_INPUT_MODE	ast_hdmitx.h	220;"	d
REG_TX_INT_CLR0	ast_hdmitx.h	100;"	d
REG_TX_INT_CLR1	ast_hdmitx.h	110;"	d
REG_TX_INT_CTRL	ast_hdmitx.h	38;"	d
REG_TX_INT_MASK1	ast_hdmitx.h	73;"	d
REG_TX_INT_MASK2	ast_hdmitx.h	81;"	d
REG_TX_INT_MASK3	ast_hdmitx.h	91;"	d
REG_TX_INT_STAT1	ast_hdmitx.h	44;"	d
REG_TX_INT_STAT2	ast_hdmitx.h	54;"	d
REG_TX_INT_STAT3	ast_hdmitx.h	64;"	d
REG_TX_ISRC1_CTRL	ast_hdmitx.h	556;"	d
REG_TX_ISRC2_CTRL	ast_hdmitx.h	557;"	d
REG_TX_MPG_INFOFRM_CTRL	ast_hdmitx.h	561;"	d
REG_TX_NULL_CTRL	ast_hdmitx.h	554;"	d
REG_TX_OESS_CYCLE	ast_hdmitx.h	314;"	d
REG_TX_PKG_MPGINFO_DB0	ast_hdmitx.h	660;"	d
REG_TX_PKG_MPGINFO_DB1	ast_hdmitx.h	661;"	d
REG_TX_PKG_MPGINFO_DB2	ast_hdmitx.h	662;"	d
REG_TX_PKG_MPGINFO_DB3	ast_hdmitx.h	663;"	d
REG_TX_PKG_MPGINFO_SUM	ast_hdmitx.h	664;"	d
REG_TX_PKT_AUDINFO_CA	ast_hdmitx.h	621;"	d
REG_TX_PKT_AUDINFO_CC	ast_hdmitx.h	619;"	d
REG_TX_PKT_AUDINFO_DM_LSV	ast_hdmitx.h	623;"	d
REG_TX_PKT_AUDINFO_SF	ast_hdmitx.h	620;"	d
REG_TX_PKT_AUDINFO_SUM	ast_hdmitx.h	624;"	d
REG_TX_PKT_GENERAL_CTRL	ast_hdmitx.h	312;"	d
REG_TX_PKT_HB00	ast_hdmitx.h	571;"	d
REG_TX_PKT_HB01	ast_hdmitx.h	572;"	d
REG_TX_PKT_HB02	ast_hdmitx.h	573;"	d
REG_TX_PKT_MPGINFO_FMT	ast_hdmitx.h	654;"	d
REG_TX_PKT_PB00	ast_hdmitx.h	575;"	d
REG_TX_PKT_PB01	ast_hdmitx.h	576;"	d
REG_TX_PKT_PB02	ast_hdmitx.h	577;"	d
REG_TX_PKT_PB03	ast_hdmitx.h	578;"	d
REG_TX_PKT_PB04	ast_hdmitx.h	579;"	d
REG_TX_PKT_PB05	ast_hdmitx.h	580;"	d
REG_TX_PKT_PB06	ast_hdmitx.h	581;"	d
REG_TX_PKT_PB07	ast_hdmitx.h	582;"	d
REG_TX_PKT_PB08	ast_hdmitx.h	583;"	d
REG_TX_PKT_PB09	ast_hdmitx.h	584;"	d
REG_TX_PKT_PB10	ast_hdmitx.h	585;"	d
REG_TX_PKT_PB11	ast_hdmitx.h	586;"	d
REG_TX_PKT_PB12	ast_hdmitx.h	587;"	d
REG_TX_PKT_PB13	ast_hdmitx.h	588;"	d
REG_TX_PKT_PB14	ast_hdmitx.h	589;"	d
REG_TX_PKT_PB15	ast_hdmitx.h	590;"	d
REG_TX_PKT_PB16	ast_hdmitx.h	591;"	d
REG_TX_PKT_PB17	ast_hdmitx.h	592;"	d
REG_TX_PKT_PB18	ast_hdmitx.h	593;"	d
REG_TX_PKT_PB19	ast_hdmitx.h	594;"	d
REG_TX_PKT_PB20	ast_hdmitx.h	595;"	d
REG_TX_PKT_PB21	ast_hdmitx.h	596;"	d
REG_TX_PKT_PB22	ast_hdmitx.h	597;"	d
REG_TX_PKT_PB23	ast_hdmitx.h	598;"	d
REG_TX_PKT_PB24	ast_hdmitx.h	599;"	d
REG_TX_PKT_PB25	ast_hdmitx.h	600;"	d
REG_TX_PKT_PB26	ast_hdmitx.h	601;"	d
REG_TX_PKT_PB27	ast_hdmitx.h	602;"	d
REG_TX_PKT_SINGLE_CTRL	ast_hdmitx.h	549;"	d
REG_TX_PKT_SPDINFO_PB1	ast_hdmitx.h	628;"	d
REG_TX_PKT_SPDINFO_PB10	ast_hdmitx.h	637;"	d
REG_TX_PKT_SPDINFO_PB11	ast_hdmitx.h	638;"	d
REG_TX_PKT_SPDINFO_PB12	ast_hdmitx.h	639;"	d
REG_TX_PKT_SPDINFO_PB13	ast_hdmitx.h	640;"	d
REG_TX_PKT_SPDINFO_PB14	ast_hdmitx.h	641;"	d
REG_TX_PKT_SPDINFO_PB15	ast_hdmitx.h	642;"	d
REG_TX_PKT_SPDINFO_PB16	ast_hdmitx.h	643;"	d
REG_TX_PKT_SPDINFO_PB17	ast_hdmitx.h	644;"	d
REG_TX_PKT_SPDINFO_PB18	ast_hdmitx.h	645;"	d
REG_TX_PKT_SPDINFO_PB19	ast_hdmitx.h	646;"	d
REG_TX_PKT_SPDINFO_PB2	ast_hdmitx.h	629;"	d
REG_TX_PKT_SPDINFO_PB20	ast_hdmitx.h	647;"	d
REG_TX_PKT_SPDINFO_PB21	ast_hdmitx.h	648;"	d
REG_TX_PKT_SPDINFO_PB22	ast_hdmitx.h	649;"	d
REG_TX_PKT_SPDINFO_PB23	ast_hdmitx.h	650;"	d
REG_TX_PKT_SPDINFO_PB24	ast_hdmitx.h	651;"	d
REG_TX_PKT_SPDINFO_PB25	ast_hdmitx.h	652;"	d
REG_TX_PKT_SPDINFO_PB3	ast_hdmitx.h	630;"	d
REG_TX_PKT_SPDINFO_PB4	ast_hdmitx.h	631;"	d
REG_TX_PKT_SPDINFO_PB5	ast_hdmitx.h	632;"	d
REG_TX_PKT_SPDINFO_PB6	ast_hdmitx.h	633;"	d
REG_TX_PKT_SPDINFO_PB7	ast_hdmitx.h	634;"	d
REG_TX_PKT_SPDINFO_PB8	ast_hdmitx.h	635;"	d
REG_TX_PKT_SPDINFO_PB9	ast_hdmitx.h	636;"	d
REG_TX_PKT_SPDINFO_SUM	ast_hdmitx.h	627;"	d
REG_TX_ROM_HEADER	ast_hdmitx.h	169;"	d
REG_TX_ROM_STARTADDR	ast_hdmitx.h	167;"	d
REG_TX_ROM_STAT	ast_hdmitx.h	171;"	d
REG_TX_SHA_RD_BYTE1	ast_hdmitx.h	196;"	d
REG_TX_SHA_RD_BYTE2	ast_hdmitx.h	197;"	d
REG_TX_SHA_RD_BYTE3	ast_hdmitx.h	198;"	d
REG_TX_SHA_RD_BYTE4	ast_hdmitx.h	199;"	d
REG_TX_SHA_SEL	ast_hdmitx.h	195;"	d
REG_TX_SPD_INFOFRM_CTRL	ast_hdmitx.h	560;"	d
REG_TX_SW_RST	ast_hdmitx.h	29;"	d
REG_TX_SYS_STATUS	ast_hdmitx.h	120;"	d
REG_TX_TXFIFO_RST	ast_hdmitx.h	232;"	d
REG_TX_VENDOR_ID0	ast_hdmitx.h	19;"	d
REG_TX_VENDOR_ID1	ast_hdmitx.h	20;"	d
REG_TX_VSE1	ast_hdmitx.h	286;"	d
REG_TX_VSE2	ast_hdmitx.h	288;"	d
REG_TX_VSS1	ast_hdmitx.h	285;"	d
REG_TX_VSS2	ast_hdmitx.h	287;"	d
ReadEDID_HDMITX_Table	ast_hdmitx.c	/^RegSetEntry ReadEDID_HDMITX_Table[] = {$/;"	v
RefCLK25MHz	ast_drv.h	/^	bool RefCLK25MHz;	$/;"	m	struct:ast_private
RegSetEntry	ast_hdmitx.h	/^} RegSetEntry;$/;"	t	typeref:struct:structRegSetEntry
SIZEOF_CSCGAIN	ast_hdmitx.h	246;"	d
SIZEOF_CSCMTX	ast_hdmitx.h	245;"	d
SIZEOF_CSCOFFSET	ast_hdmitx.h	247;"	d
SetI2CReg	ast_hdmitx.c	/^static void SetI2CReg(struct drm_device *dev, u8 jChannel, u8 DeviceAddr, u8 jIndex, u8 jData )$/;"	f	file:
Side_by_Side	ast_hdmitx.h	668;"	d
Switch_HDMITX_Bank	ast_hdmitx.h	320;"	d
SyncNN	ast_tables.h	49;"	d
SyncNP	ast_tables.h	48;"	d
SyncPN	ast_tables.h	47;"	d
SyncPP	ast_tables.h	46;"	d
TIMEOUT	ast_post.c	443;"	d	file:
TIMEOUT_AST2150	ast_post.c	149;"	d	file:
TMDSClock	ast_hdmitx.h	/^        unsigned long TMDSClock ;$/;"	m	struct:_HDMITXDEV_STRUCT
TextModeIndex	ast_tables.h	28;"	d
Top_and_Botton	ast_hdmitx.h	667;"	d
TrueCModeIndex	ast_tables.h	32;"	d
TxEMEMStatus	ast_hdmitx.h	/^        u8 TxEMEMStatus:1 ;$/;"	m	struct:_HDMITXDEV_STRUCT
UNKNOWN_MODE	ast_hdmitx.h	/^    UNKNOWN_MODE=0,$/;"	e	enum:_mode_id
VBorder	ast_tables.h	39;"	d
VCLK106_5	ast_tables.h	72;"	d
VCLK108	ast_tables.h	65;"	d
VCLK118_25	ast_tables.h	80;"	d
VCLK119	ast_tables.h	77;"	d
VCLK135	ast_tables.h	66;"	d
VCLK146_25	ast_tables.h	73;"	d
VCLK148_5	ast_tables.h	74;"	d
VCLK154	ast_tables.h	70;"	d
VCLK157_5	ast_tables.h	67;"	d
VCLK162	ast_tables.h	68;"	d
VCLK25_175	ast_tables.h	53;"	d
VCLK28_322	ast_tables.h	54;"	d
VCLK31_5	ast_tables.h	55;"	d
VCLK36	ast_tables.h	56;"	d
VCLK40	ast_tables.h	57;"	d
VCLK49_5	ast_tables.h	58;"	d
VCLK50	ast_tables.h	59;"	d
VCLK56_25	ast_tables.h	60;"	d
VCLK65	ast_tables.h	61;"	d
VCLK71	ast_tables.h	75;"	d
VCLK75	ast_tables.h	62;"	d
VCLK78_75	ast_tables.h	63;"	d
VCLK83_5	ast_tables.h	71;"	d
VCLK85_5	ast_tables.h	78;"	d
VCLK88_75	ast_tables.h	76;"	d
VCLK94_5	ast_tables.h	64;"	d
VCLK97_75	ast_tables.h	79;"	d
VESA_1024x768p60	ast_hdmitx.h	/^    VESA_1024x768p60,$/;"	e	enum:_mode_id
VESA_1024x768p70	ast_hdmitx.h	/^    VESA_1024x768p70,$/;"	e	enum:_mode_id
VESA_1024x768p75	ast_hdmitx.h	/^    VESA_1024x768p75,$/;"	e	enum:_mode_id
VESA_1024x768p85	ast_hdmitx.h	/^    VESA_1024x768p85,$/;"	e	enum:_mode_id
VESA_1152x864p75	ast_hdmitx.h	/^    VESA_1152x864p75,$/;"	e	enum:_mode_id
VESA_1280X1024p85	ast_hdmitx.h	/^    VESA_1280X1024p85,$/;"	e	enum:_mode_id
VESA_1280x1024p60	ast_hdmitx.h	/^    VESA_1280x1024p60,$/;"	e	enum:_mode_id
VESA_1280x1024p75	ast_hdmitx.h	/^    VESA_1280x1024p75,$/;"	e	enum:_mode_id
VESA_1280x768p60	ast_hdmitx.h	/^    VESA_1280x768p60,$/;"	e	enum:_mode_id
VESA_1280x768p60R	ast_hdmitx.h	/^    VESA_1280x768p60R,$/;"	e	enum:_mode_id
VESA_1280x768p75	ast_hdmitx.h	/^    VESA_1280x768p75,$/;"	e	enum:_mode_id
VESA_1280x768p85	ast_hdmitx.h	/^    VESA_1280x768p85,$/;"	e	enum:_mode_id
VESA_1280x960p60	ast_hdmitx.h	/^    VESA_1280x960p60,$/;"	e	enum:_mode_id
VESA_1280x960p85	ast_hdmitx.h	/^    VESA_1280x960p85,$/;"	e	enum:_mode_id
VESA_1360X768p60	ast_hdmitx.h	/^    VESA_1360X768p60,$/;"	e	enum:_mode_id
VESA_1400x1050p75	ast_hdmitx.h	/^    VESA_1400x1050p75,$/;"	e	enum:_mode_id
VESA_1400x1050p85	ast_hdmitx.h	/^    VESA_1400x1050p85,$/;"	e	enum:_mode_id
VESA_1400x768p60	ast_hdmitx.h	/^    VESA_1400x768p60,$/;"	e	enum:_mode_id
VESA_1400x768p60R	ast_hdmitx.h	/^    VESA_1400x768p60R,$/;"	e	enum:_mode_id
VESA_1440x900p60	ast_hdmitx.h	/^    VESA_1440x900p60,$/;"	e	enum:_mode_id
VESA_1440x900p60R	ast_hdmitx.h	/^    VESA_1440x900p60R,$/;"	e	enum:_mode_id
VESA_1440x900p75	ast_hdmitx.h	/^    VESA_1440x900p75,$/;"	e	enum:_mode_id
VESA_1440x900p85	ast_hdmitx.h	/^    VESA_1440x900p85,$/;"	e	enum:_mode_id
VESA_1600x1200p60	ast_hdmitx.h	/^    VESA_1600x1200p60,$/;"	e	enum:_mode_id
VESA_1600x1200p65	ast_hdmitx.h	/^    VESA_1600x1200p65,$/;"	e	enum:_mode_id
VESA_1600x1200p70	ast_hdmitx.h	/^    VESA_1600x1200p70,$/;"	e	enum:_mode_id
VESA_1600x1200p75	ast_hdmitx.h	/^    VESA_1600x1200p75,$/;"	e	enum:_mode_id
VESA_1600x1200p85	ast_hdmitx.h	/^    VESA_1600x1200p85,$/;"	e	enum:_mode_id
VESA_1680x1050p60	ast_hdmitx.h	/^    VESA_1680x1050p60,$/;"	e	enum:_mode_id
VESA_1680x1050p60R	ast_hdmitx.h	/^    VESA_1680x1050p60R,$/;"	e	enum:_mode_id
VESA_1680x1050p75	ast_hdmitx.h	/^    VESA_1680x1050p75,$/;"	e	enum:_mode_id
VESA_1680x1050p85	ast_hdmitx.h	/^    VESA_1680x1050p85,$/;"	e	enum:_mode_id
VESA_1792x1344p60	ast_hdmitx.h	/^    VESA_1792x1344p60,$/;"	e	enum:_mode_id
VESA_1792x1344p75	ast_hdmitx.h	/^    VESA_1792x1344p75,$/;"	e	enum:_mode_id
VESA_1856x1392p60	ast_hdmitx.h	/^    VESA_1856x1392p60,$/;"	e	enum:_mode_id
VESA_1856x1392p75	ast_hdmitx.h	/^    VESA_1856x1392p75,$/;"	e	enum:_mode_id
VESA_1920x1200p60	ast_hdmitx.h	/^    VESA_1920x1200p60,$/;"	e	enum:_mode_id
VESA_1920x1200p60R	ast_hdmitx.h	/^    VESA_1920x1200p60R,$/;"	e	enum:_mode_id
VESA_1920x1200p75	ast_hdmitx.h	/^    VESA_1920x1200p75,$/;"	e	enum:_mode_id
VESA_1920x1200p85	ast_hdmitx.h	/^    VESA_1920x1200p85,$/;"	e	enum:_mode_id
VESA_1920x1440p60	ast_hdmitx.h	/^    VESA_1920x1440p60,$/;"	e	enum:_mode_id
VESA_1920x1440p75	ast_hdmitx.h	/^    VESA_1920x1440p75,$/;"	e	enum:_mode_id
VESA_640x350p85	ast_hdmitx.h	/^    VESA_640x350p85,$/;"	e	enum:_mode_id
VESA_640x400p85	ast_hdmitx.h	/^    VESA_640x400p85,$/;"	e	enum:_mode_id
VESA_640x480p60	ast_hdmitx.h	/^    VESA_640x480p60,$/;"	e	enum:_mode_id
VESA_640x480p72	ast_hdmitx.h	/^    VESA_640x480p72,$/;"	e	enum:_mode_id
VESA_640x480p75	ast_hdmitx.h	/^    VESA_640x480p75,$/;"	e	enum:_mode_id
VESA_640x480p85	ast_hdmitx.h	/^    VESA_640x480p85,$/;"	e	enum:_mode_id
VESA_720x400p85	ast_hdmitx.h	/^    VESA_720x400p85,$/;"	e	enum:_mode_id
VESA_800X600p85	ast_hdmitx.h	/^    VESA_800X600p85,$/;"	e	enum:_mode_id
VESA_800x600p56	ast_hdmitx.h	/^    VESA_800x600p56,$/;"	e	enum:_mode_id
VESA_800x600p60	ast_hdmitx.h	/^    VESA_800x600p60,$/;"	e	enum:_mode_id
VESA_800x600p72	ast_hdmitx.h	/^    VESA_800x600p72,$/;"	e	enum:_mode_id
VESA_800x600p75	ast_hdmitx.h	/^    VESA_800x600p75,$/;"	e	enum:_mode_id
VESA_840X480p60	ast_hdmitx.h	/^    VESA_840X480p60,$/;"	e	enum:_mode_id
VGAModeIndex	ast_tables.h	30;"	d
VIDEOPCLKLEVEL	ast_hdmitx.h	/^} VIDEOPCLKLEVEL ;$/;"	t	typeref:enum:__anon3
WideScreenMode	ast_tables.h	40;"	d
_80MHz	ast_hdmitx.h	11;"	d
_HDMITXDEV_STRUCT	ast_hdmitx.h	/^typedef struct _HDMITXDEV_STRUCT {$/;"	s
__AST_DRV_H__	ast_drv.h	29;"	d
__ast_io_read	ast_drv.h	179;"	d
__ast_io_write	ast_drv.h	199;"	d
__ast_io_write	ast_drv.h	206;"	d
__ast_read	ast_drv.h	168;"	d
__ast_write	ast_drv.h	190;"	d
_mode_id	ast_hdmitx.h	/^typedef enum _mode_id {$/;"	g
adapter	ast_drv.h	/^	struct i2c_adapter adapter;$/;"	m	struct:ast_i2c_chan	typeref:struct:ast_i2c_chan::i2c_adapter
ar	ast_drv.h	/^	u8 ar[20];$/;"	m	struct:ast_vbios_stdtable
ast-objs	Makefile	/^    ast-objs := ast_drv.o ast_main.o ast_mode.o ast_ttm.o ast_post.o ast_dp501.o ast_dp.o ast_hdmitx.o$/;"	m
ast1100_dram_table_data	ast_dram_tables.h	/^static const struct ast_dramstruct ast1100_dram_table_data[] = {$/;"	v	typeref:struct:ast_dramstruct
ast2000_dram_table_data	ast_dram_tables.h	/^static const struct ast_dramstruct ast2000_dram_table_data[] = {$/;"	v	typeref:struct:ast_dramstruct
ast2100_dram_table_data	ast_dram_tables.h	/^static const struct ast_dramstruct ast2100_dram_table_data[] = {$/;"	v	typeref:struct:ast_dramstruct
ast2300_dram_param	ast_post.c	/^struct ast2300_dram_param {$/;"	s	file:
ast2500_ddr3_1600_timing_table	ast_dram_tables.h	/^static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {$/;"	v
ast2500_ddr4_1600_timing_table	ast_dram_tables.h	/^static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {$/;"	v
ast_backup_fw	ast_dp501.c	/^bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size)$/;"	f
ast_chip	ast_drv.h	/^enum ast_chip {$/;"	g
ast_connector	ast_drv.h	/^struct ast_connector {$/;"	s
ast_connector_destroy	ast_mode.c	/^static void ast_connector_destroy(struct drm_connector *connector)$/;"	f	file:
ast_connector_funcs	ast_mode.c	/^static const struct drm_connector_funcs ast_connector_funcs = {$/;"	v	typeref:struct:drm_connector_funcs	file:
ast_connector_helper_funcs	ast_mode.c	/^static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {$/;"	v	typeref:struct:drm_connector_helper_funcs	file:
ast_connector_init	ast_mode.c	/^static int ast_connector_init(struct drm_device *dev)$/;"	f	file:
ast_crtc	ast_drv.h	/^struct ast_crtc {$/;"	s
ast_crtc_atomic_destroy_state	ast_mode.c	/^static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc,$/;"	f	file:
ast_crtc_atomic_duplicate_state	ast_mode.c	/^ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc)$/;"	f	file:
ast_crtc_destroy	ast_mode.c	/^static void ast_crtc_destroy(struct drm_crtc *crtc)$/;"	f	file:
ast_crtc_dpms	ast_mode.c	/^static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)$/;"	f	file:
ast_crtc_funcs	ast_mode.c	/^static const struct drm_crtc_funcs ast_crtc_funcs = {$/;"	v	typeref:struct:drm_crtc_funcs	file:
ast_crtc_helper_atomic_begin	ast_mode.c	/^static void ast_crtc_helper_atomic_begin(struct drm_crtc *crtc,$/;"	f	file:
ast_crtc_helper_atomic_check	ast_mode.c	/^static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,$/;"	f	file:
ast_crtc_helper_atomic_disable	ast_mode.c	/^ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,$/;"	f	file:
ast_crtc_helper_atomic_enable	ast_mode.c	/^ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,$/;"	f	file:
ast_crtc_helper_atomic_flush	ast_mode.c	/^static void ast_crtc_helper_atomic_flush(struct drm_crtc *crtc,$/;"	f	file:
ast_crtc_helper_funcs	ast_mode.c	/^static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {$/;"	v	typeref:struct:drm_crtc_helper_funcs	file:
ast_crtc_init	ast_mode.c	/^static int ast_crtc_init(struct drm_device *dev)$/;"	f	file:
ast_crtc_load_lut	ast_mode.c	/^static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc)$/;"	f	file:
ast_crtc_reset	ast_mode.c	/^static void ast_crtc_reset(struct drm_crtc *crtc)$/;"	f	file:
ast_crtc_state	ast_drv.h	/^struct ast_crtc_state {$/;"	s
ast_cursor_fini	ast_mode.c	/^static void ast_cursor_fini(struct drm_device *dev)$/;"	f	file:
ast_cursor_init	ast_mode.c	/^static int ast_cursor_init(struct drm_device *dev)$/;"	f	file:
ast_cursor_move	ast_mode.c	/^static int ast_cursor_move(struct drm_crtc *crtc,$/;"	f	file:
ast_cursor_plane_formats	ast_mode.c	/^static const uint32_t ast_cursor_plane_formats[] = {$/;"	v	file:
ast_cursor_plane_funcs	ast_mode.c	/^static const struct drm_plane_funcs ast_cursor_plane_funcs = {$/;"	v	typeref:struct:drm_plane_funcs	file:
ast_cursor_plane_helper_atomic_check	ast_mode.c	/^static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,$/;"	f	file:
ast_cursor_plane_helper_atomic_disable	ast_mode.c	/^ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane,$/;"	f	file:
ast_cursor_plane_helper_atomic_update	ast_mode.c	/^ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,$/;"	f	file:
ast_cursor_plane_helper_funcs	ast_mode.c	/^static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = {$/;"	v	typeref:struct:drm_plane_helper_funcs	file:
ast_cursor_plane_helper_prepare_fb	ast_mode.c	/^ast_cursor_plane_helper_prepare_fb(struct drm_plane *plane,$/;"	f	file:
ast_cursor_set_base	ast_mode.c	/^static void ast_cursor_set_base(struct ast_private *ast, u64 address)$/;"	f	file:
ast_cursor_update	ast_mode.c	/^static int ast_cursor_update(void *dst, void *src, unsigned int width,$/;"	f	file:
ast_detect_chip	ast_main.c	/^static int ast_detect_chip(struct drm_device *dev, bool *need_post)$/;"	f	file:
ast_detect_config_mode	ast_main.c	/^static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)$/;"	f	file:
ast_dp501_read_edid	ast_dp501.c	/^bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata)$/;"	f
ast_dp_PowerOnOff	ast_dp.c	/^void ast_dp_PowerOnOff(struct drm_device *dev, u8 Mode)$/;"	f
ast_dp_SetOnOff	ast_dp.c	/^void ast_dp_SetOnOff(struct drm_device *dev, u8 Mode)$/;"	f
ast_dp_SetOutput	ast_dp.c	/^void ast_dp_SetOutput(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode)$/;"	f
ast_dp_launch	ast_dp.c	/^bool ast_dp_launch(struct drm_device *dev, u8 bPower)$/;"	f
ast_dp_read_edid	ast_dp.c	/^bool ast_dp_read_edid(struct drm_device *dev, u8 *ediddata)$/;"	f
ast_dram_init_2500	ast_post.c	/^static bool ast_dram_init_2500(struct ast_private *ast)$/;"	f	file:
ast_dramstruct	ast_dram_tables.h	/^struct ast_dramstruct {$/;"	s
ast_driver_load	ast_main.c	/^int ast_driver_load(struct drm_device *dev, unsigned long flags)$/;"	f
ast_driver_unload	ast_main.c	/^void ast_driver_unload(struct drm_device *dev)$/;"	f
ast_drm_freeze	ast_drv.c	/^static int ast_drm_freeze(struct drm_device *dev)$/;"	f	file:
ast_drm_resume	ast_drv.c	/^static int ast_drm_resume(struct drm_device *dev)$/;"	f	file:
ast_drm_thaw	ast_drv.c	/^static int ast_drm_thaw(struct drm_device *dev)$/;"	f	file:
ast_enable_mmio	ast_post.c	/^void ast_enable_mmio(struct drm_device *dev)$/;"	f
ast_enable_vga	ast_post.c	/^void ast_enable_vga(struct drm_device *dev)$/;"	f
ast_encoder_init	ast_mode.c	/^static int ast_encoder_init(struct drm_device *dev)$/;"	f	file:
ast_exit	ast_drv.c	/^module_exit(ast_exit);$/;"	v
ast_exit	ast_drv.c	/^static void __exit ast_exit(void)$/;"	f	file:
ast_fops	ast_drv.c	/^DEFINE_DRM_GEM_FOPS(ast_fops);$/;"	v
ast_get_dp501_max_clk	ast_dp501.c	/^u8 ast_get_dp501_max_clk(struct drm_device *dev)$/;"	f
ast_get_dram_info	ast_main.c	/^static int ast_get_dram_info(struct drm_device *dev)$/;"	f	file:
ast_get_index_reg	ast_main.c	/^uint8_t ast_get_index_reg(struct ast_private *ast,$/;"	f
ast_get_index_reg_mask	ast_main.c	/^uint8_t ast_get_index_reg_mask(struct ast_private *ast,$/;"	f
ast_get_modes	ast_mode.c	/^static int ast_get_modes(struct drm_connector *connector)$/;"	f	file:
ast_get_vbios_mode_info	ast_mode.c	/^static bool ast_get_vbios_mode_info(const struct drm_format_info *format,$/;"	f	file:
ast_get_vram_info	ast_main.c	/^static u32 ast_get_vram_info(struct drm_device *dev)$/;"	f	file:
ast_hdmi_check	ast_hdmitx.c	/^bool ast_hdmi_check(struct drm_device *dev)$/;"	f
ast_hdmi_disable	ast_hdmitx.c	/^void ast_hdmi_disable(struct drm_device *dev)$/;"	f
ast_hdmi_init	ast_hdmitx.c	/^void ast_hdmi_init(struct drm_device *dev)$/;"	f
ast_hdmi_read_edid	ast_hdmitx.c	/^bool ast_hdmi_read_edid(struct drm_device *dev, u8 *pEDIDData)$/;"	f
ast_hdmi_set_output	ast_hdmitx.c	/^void ast_hdmi_set_output(struct drm_device *dev)$/;"	f
ast_i2c_chan	ast_drv.h	/^struct ast_i2c_chan {$/;"	s
ast_i2c_create	ast_mode.c	/^static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)$/;"	f	file:
ast_i2c_destroy	ast_mode.c	/^static void ast_i2c_destroy(struct ast_i2c_chan *i2c)$/;"	f	file:
ast_init	ast_drv.c	/^module_init(ast_init);$/;"	v
ast_init	ast_drv.c	/^static int __init ast_init(void)$/;"	f	file:
ast_init_3rdtx	ast_dp501.c	/^void ast_init_3rdtx(struct drm_device *dev)$/;"	f
ast_init_analog	ast_dp501.c	/^static void ast_init_analog(struct drm_device *dev)$/;"	f	file:
ast_init_dram_reg	ast_post.c	/^static void ast_init_dram_reg(struct drm_device *dev)$/;"	f	file:
ast_init_dvo	ast_dp501.c	/^static bool ast_init_dvo(struct drm_device *dev)$/;"	f	file:
ast_is_vga_enabled	ast_post.c	/^bool ast_is_vga_enabled(struct drm_device *dev)$/;"	f
ast_kick_out_firmware_fb	ast_drv.c	/^static void ast_kick_out_firmware_fb(struct pci_dev *pdev)$/;"	f	file:
ast_launch_m68k	ast_dp501.c	/^static bool ast_launch_m68k(struct drm_device *dev)$/;"	f	file:
ast_load_dp501_microcode	ast_dp501.c	/^static int ast_load_dp501_microcode(struct drm_device *dev)$/;"	f	file:
ast_load_palette_index	ast_mode.c	/^static inline void ast_load_palette_index(struct ast_private *ast,$/;"	f	file:
ast_mindwm	ast_post.c	/^u32 ast_mindwm(struct ast_private *ast, u32 r)$/;"	f
ast_mm_fini	ast_ttm.c	/^void ast_mm_fini(struct ast_private *ast)$/;"	f
ast_mm_init	ast_ttm.c	/^int ast_mm_init(struct ast_private *ast)$/;"	f
ast_mode_fini	ast_mode.c	/^void ast_mode_fini(struct drm_device *dev)$/;"	f
ast_mode_funcs	ast_main.c	/^static const struct drm_mode_config_funcs ast_mode_funcs = {$/;"	v	typeref:struct:drm_mode_config_funcs	file:
ast_mode_init	ast_mode.c	/^int ast_mode_init(struct drm_device *dev)$/;"	f
ast_mode_valid	ast_mode.c	/^static enum drm_mode_status ast_mode_valid(struct drm_connector *connector,$/;"	f	file:
ast_modeset	ast_drv.c	/^int ast_modeset = -1;$/;"	v
ast_moutdwm	ast_post.c	/^void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)$/;"	f
ast_open_key	ast_drv.h	/^static inline void ast_open_key(struct ast_private *ast)$/;"	f
ast_pci_driver	ast_drv.c	/^static struct pci_driver ast_pci_driver = {$/;"	v	typeref:struct:pci_driver	file:
ast_pci_probe	ast_drv.c	/^static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)$/;"	f	file:
ast_pci_remove	ast_drv.c	/^ast_pci_remove(struct pci_dev *pdev)$/;"	f	file:
ast_pm_freeze	ast_drv.c	/^static int ast_pm_freeze(struct device *dev)$/;"	f	file:
ast_pm_ops	ast_drv.c	/^static const struct dev_pm_ops ast_pm_ops = {$/;"	v	typeref:struct:dev_pm_ops	file:
ast_pm_poweroff	ast_drv.c	/^static int ast_pm_poweroff(struct device *dev)$/;"	f	file:
ast_pm_resume	ast_drv.c	/^static int ast_pm_resume(struct device *dev)$/;"	f	file:
ast_pm_suspend	ast_drv.c	/^static int ast_pm_suspend(struct device *dev)$/;"	f	file:
ast_pm_thaw	ast_drv.c	/^static int ast_pm_thaw(struct device *dev)$/;"	f	file:
ast_post_chip_2300	ast_post.c	/^static void ast_post_chip_2300(struct drm_device *dev)$/;"	f	file:
ast_post_chip_2500	ast_post.c	/^void ast_post_chip_2500(struct drm_device *dev)$/;"	f
ast_post_gpu	ast_post.c	/^void ast_post_gpu(struct drm_device *dev)$/;"	f
ast_primary_plane_formats	ast_mode.c	/^static const uint32_t ast_primary_plane_formats[] = {$/;"	v	file:
ast_primary_plane_funcs	ast_mode.c	/^static const struct drm_plane_funcs ast_primary_plane_funcs = {$/;"	v	typeref:struct:drm_plane_funcs	file:
ast_primary_plane_helper_atomic_check	ast_mode.c	/^static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,$/;"	f	file:
ast_primary_plane_helper_atomic_disable	ast_mode.c	/^ast_primary_plane_helper_atomic_disable(struct drm_plane *plane,$/;"	f	file:
ast_primary_plane_helper_atomic_update	ast_mode.c	/^ast_primary_plane_helper_atomic_update(struct drm_plane *plane,$/;"	f	file:
ast_primary_plane_helper_funcs	ast_mode.c	/^static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = {$/;"	v	typeref:struct:drm_plane_helper_funcs	file:
ast_private	ast_drv.h	/^struct ast_private {$/;"	s
ast_release_firmware	ast_dp501.c	/^void ast_release_firmware(struct drm_device *dev)$/;"	f
ast_set_color_reg	ast_mode.c	/^static void ast_set_color_reg(struct ast_private *ast,$/;"	f	file:
ast_set_crtc_reg	ast_mode.c	/^static void ast_set_crtc_reg(struct ast_private *ast,$/;"	f	file:
ast_set_crtthd_reg	ast_mode.c	/^static void ast_set_crtthd_reg(struct ast_private *ast)$/;"	f	file:
ast_set_dclk_reg	ast_mode.c	/^static void ast_set_dclk_reg(struct ast_private *ast,$/;"	f	file:
ast_set_def_ext_reg	ast_post.c	/^ast_set_def_ext_reg(struct drm_device *dev)$/;"	f	file:
ast_set_dp501_video_output	ast_dp501.c	/^void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)$/;"	f
ast_set_index_reg	ast_drv.h	/^static inline void ast_set_index_reg(struct ast_private *ast,$/;"	f
ast_set_index_reg_mask	ast_main.c	/^void ast_set_index_reg_mask(struct ast_private *ast,$/;"	f
ast_set_offset_reg	ast_mode.c	/^static void ast_set_offset_reg(struct ast_private *ast,$/;"	f	file:
ast_set_start_address_crt1	ast_mode.c	/^static void ast_set_start_address_crt1(struct ast_private *ast,$/;"	f	file:
ast_set_std_reg	ast_mode.c	/^static void ast_set_std_reg(struct ast_private *ast,$/;"	f	file:
ast_set_sync_reg	ast_mode.c	/^static void ast_set_sync_reg(struct ast_private *ast,$/;"	f	file:
ast_set_vbios_color_reg	ast_mode.c	/^static void ast_set_vbios_color_reg(struct ast_private *ast,$/;"	f	file:
ast_set_vbios_mode_reg	ast_mode.c	/^static void ast_set_vbios_mode_reg(struct ast_private *ast,$/;"	f	file:
ast_tx_chip	ast_drv.h	/^enum ast_tx_chip {$/;"	g
ast_use_defaults	ast_drv.h	/^		ast_use_defaults$/;"	e	enum:ast_private::__anon2
ast_use_dt	ast_drv.h	/^		ast_use_dt,$/;"	e	enum:ast_private::__anon2
ast_use_p2a	ast_drv.h	/^		ast_use_p2a,$/;"	e	enum:ast_private::__anon2
ast_vbios_dclk_info	ast_drv.h	/^struct ast_vbios_dclk_info {$/;"	s
ast_vbios_enhtable	ast_drv.h	/^struct ast_vbios_enhtable {$/;"	s
ast_vbios_mode_info	ast_drv.h	/^struct ast_vbios_mode_info {$/;"	s
ast_vbios_stdtable	ast_drv.h	/^struct ast_vbios_stdtable {$/;"	s
ast_wait_one_vsync	ast_main.c	/^void inline ast_wait_one_vsync(struct ast_private *ast)$/;"	f
ast_write_cmd	ast_dp501.c	/^static bool ast_write_cmd(struct drm_device *dev, u8 data)$/;"	f	file:
ast_write_data	ast_dp501.c	/^static bool ast_write_data(struct drm_device *dev, u8 data)$/;"	f	file:
bAudFs	ast_hdmitx.h	/^        u8 bAudFs ;$/;"	m	struct:_HDMITXDEV_STRUCT
bAudioChannelEnable	ast_hdmitx.h	/^        u8 bAudioChannelEnable ;$/;"	m	struct:_HDMITXDEV_STRUCT
bAudioChannelSwap	ast_hdmitx.h	/^	u8 bAudioChannelSwap ; \/*  = 0 ; *\/$/;"	m	struct:_HDMITXDEV_STRUCT
bAuthenticated	ast_hdmitx.h	/^	u8 bAuthenticated:1 ;$/;"	m	struct:_HDMITXDEV_STRUCT
bHDMIMode	ast_hdmitx.h	/^	u8 bHDMIMode: 1;$/;"	m	struct:_HDMITXDEV_STRUCT
bHPD	ast_hdmitx.h	/^	u8 bHPD:1 ;$/;"	m	struct:_HDMITXDEV_STRUCT
bInputVideoSignalType	ast_hdmitx.h	/^	u8 bInputVideoSignalType ; \/* for Sync Embedded,CCIR656,InputDDR *\/$/;"	m	struct:_HDMITXDEV_STRUCT
bIntPOL	ast_hdmitx.h	/^	u8 bIntPOL:1 ; \/* 0 = Low Active *\/$/;"	m	struct:_HDMITXDEV_STRUCT
bIntType	ast_hdmitx.h	/^	u8 bIntType ; \/* = 0 ; *\/$/;"	m	struct:_HDMITXDEV_STRUCT
bOutputAudioMode	ast_hdmitx.h	/^	u8 bOutputAudioMode ; \/* = 0 ; *\/$/;"	m	struct:_HDMITXDEV_STRUCT
bSPDIF_OUT	ast_hdmitx.h	/^        u8 bSPDIF_OUT;$/;"	m	struct:_HDMITXDEV_STRUCT
base	ast_drv.h	/^	struct drm_connector base;$/;"	m	struct:ast_connector	typeref:struct:ast_connector::drm_connector
base	ast_drv.h	/^	struct drm_crtc base;$/;"	m	struct:ast_crtc	typeref:struct:ast_crtc::drm_crtc
base	ast_drv.h	/^	struct drm_crtc_state base;$/;"	m	struct:ast_crtc_state	typeref:struct:ast_crtc_state::drm_crtc_state
bit	ast_drv.h	/^	struct i2c_algo_bit_data bit;$/;"	m	struct:ast_i2c_chan	typeref:struct:ast_i2c_chan::i2c_algo_bit_data
cbr_dll2	ast_post.c	/^static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)$/;"	f	file:
cbr_scan	ast_post.c	/^static int cbr_scan(struct ast_private *ast)$/;"	f	file:
cbr_scan2	ast_post.c	/^static u32 cbr_scan2(struct ast_private *ast)$/;"	f	file:
cbr_scan3	ast_post.c	/^static bool cbr_scan3(struct ast_private *ast)$/;"	f	file:
cbr_test	ast_post.c	/^static int cbr_test(struct ast_private *ast)$/;"	f	file:
cbr_test2	ast_post.c	/^static u32 cbr_test2(struct ast_private *ast)$/;"	f	file:
cbr_test3	ast_post.c	/^static bool cbr_test3(struct ast_private *ast)$/;"	f	file:
cbr_test_2500	ast_post.c	/^static bool cbr_test_2500(struct ast_private *ast)$/;"	f	file:
cbrdlli_ast2150	ast_post.c	/^static void cbrdlli_ast2150(struct ast_private *ast, int busw)$/;"	f	file:
cbrscan_ast2150	ast_post.c	/^static int cbrscan_ast2150(struct ast_private *ast, int busw)$/;"	f	file:
cbrtest_ast2150	ast_post.c	/^static int cbrtest_ast2150(struct ast_private *ast)$/;"	f	file:
ccflags-y	Makefile	/^ccflags-y := -Iinclude\/drm -g -O0$/;"	m
check_dram_size_2500	ast_post.c	/^static void check_dram_size_2500(struct ast_private *ast, u32 tRFC)$/;"	f	file:
chip	ast_drv.h	/^	enum ast_chip chip;$/;"	m	struct:ast_private	typeref:enum:ast_private::ast_chip
clear_cmd_trigger	ast_dp501.c	/^static void clear_cmd_trigger(struct ast_private *ast)$/;"	f	file:
config_mode	ast_drv.h	/^	} config_mode;$/;"	m	struct:ast_private	typeref:enum:ast_private::__anon2
copy_cursor_image	ast_mode.c	/^static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)$/;"	f	file:
crtc	ast_drv.h	/^	u8 crtc[25];$/;"	m	struct:ast_vbios_stdtable
cursor	ast_drv.h	/^	} cursor;$/;"	m	struct:ast_private	typeref:struct:ast_private::__anon1
cursor_plane	ast_drv.h	/^	struct drm_plane cursor_plane;$/;"	m	struct:ast_private	typeref:struct:ast_private::drm_plane
data	ast_dram_tables.h	/^	u32 data;$/;"	m	struct:ast_dramstruct
dclk_index	ast_drv.h	/^	u32 dclk_index;$/;"	m	struct:ast_vbios_enhtable
dclk_table	ast_tables.h	/^static const struct ast_vbios_dclk_info dclk_table[] = {$/;"	v	typeref:struct:ast_vbios_dclk_info
dclk_table_25MHz	ast_tables.h	/^static const struct ast_vbios_dclk_info dclk_table_25MHz[] = {$/;"	v	typeref:struct:ast_vbios_dclk_info
dclk_table_ast2500	ast_tables.h	/^static const struct ast_vbios_dclk_info dclk_table_ast2500[] = {$/;"	v	typeref:struct:ast_vbios_dclk_info
dclk_table_ast2500_25MHz	ast_tables.h	/^static const struct ast_vbios_dclk_info dclk_table_ast2500_25MHz[] = {$/;"	v	typeref:struct:ast_vbios_dclk_info
ddr2_init	ast_post.c	/^static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)$/;"	f	file:
ddr3_init	ast_post.c	/^static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)$/;"	f	file:
ddr3_init_2500	ast_post.c	/^static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)$/;"	f	file:
ddr4_init_2500	ast_post.c	/^static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table)$/;"	f	file:
ddr_init_common_2500	ast_post.c	/^static void ddr_init_common_2500(struct ast_private *ast)$/;"	f	file:
ddr_phy_init_2500	ast_post.c	/^static void ddr_phy_init_2500(struct ast_private *ast)$/;"	f	file:
ddr_test_2500	ast_post.c	/^static bool ddr_test_2500(struct ast_private *ast)$/;"	f	file:
dev	ast_drv.h	/^	struct drm_device *dev;$/;"	m	struct:ast_i2c_chan	typeref:struct:ast_i2c_chan::drm_device
dev	ast_drv.h	/^	struct drm_device *dev;$/;"	m	struct:ast_private	typeref:struct:ast_private::drm_device
dll2_finetune_step	ast_post.c	/^	u32 dll2_finetune_step;$/;"	m	struct:ast2300_dram_param	file:
dp501_fw	ast_drv.h	/^	const struct firmware *dp501_fw;	\/* dp501 fw *\/$/;"	m	struct:ast_private	typeref:struct:ast_private::firmware
dp501_fw_addr	ast_drv.h	/^	u8 *dp501_fw_addr;$/;"	m	struct:ast_private
dp501_maxclk	ast_drv.h	/^	u8 dp501_maxclk;$/;"	m	struct:ast_private
dram_bus_width	ast_drv.h	/^	uint32_t dram_bus_width;$/;"	m	struct:ast_private
dram_chipid	ast_post.c	/^	u32 dram_chipid;$/;"	m	struct:ast2300_dram_param	file:
dram_config	ast_post.c	/^	u32 dram_config;$/;"	m	struct:ast2300_dram_param	file:
dram_freq	ast_post.c	/^	u32 dram_freq;$/;"	m	struct:ast2300_dram_param	file:
dram_type	ast_drv.h	/^	uint32_t dram_type;$/;"	m	struct:ast_private
dram_type	ast_post.c	/^	u32 dram_type;$/;"	m	struct:ast2300_dram_param	file:
driver	ast_drv.c	/^static struct drm_driver driver = {$/;"	v	typeref:struct:drm_driver	file:
driver	ast_drv.c	/^static struct drm_driver driver;$/;"	v	typeref:struct:drm_driver	file:
enable_cache_2500	ast_post.c	/^static void enable_cache_2500(struct ast_private *ast)$/;"	f	file:
encoder	ast_drv.h	/^	struct drm_encoder encoder;$/;"	m	struct:ast_private	typeref:struct:ast_private::drm_encoder
enh_table	ast_drv.h	/^	const struct ast_vbios_enhtable *enh_table;$/;"	m	struct:ast_vbios_mode_info	typeref:struct:ast_vbios_mode_info::ast_vbios_enhtable
extreginfo	ast_post.c	/^static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };$/;"	v	file:
extreginfo_ast2300	ast_post.c	/^static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };$/;"	v	file:
extreginfo_ast2300a0	ast_post.c	/^static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };$/;"	v	file:
fb_mtrr	ast_drv.h	/^	int fb_mtrr;$/;"	m	struct:ast_private
finetuneDQI_L	ast_post.c	/^static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)$/;"	f	file:
finetuneDQSI	ast_post.c	/^static void finetuneDQSI(struct ast_private *ast)$/;"	f	file:
flags	ast_drv.h	/^	u32 flags;$/;"	m	struct:ast_vbios_enhtable
format	ast_drv.h	/^	const struct drm_format_info *format;$/;"	m	struct:ast_crtc_state	typeref:struct:ast_crtc_state::drm_format_info
gbo	ast_drv.h	/^		struct drm_gem_vram_object *gbo[AST_DEFAULT_HWC_NUM];$/;"	m	struct:ast_private::__anon1	typeref:struct:ast_private::__anon1::drm_gem_vram_object
get_clock	ast_mode.c	/^static int get_clock(void *i2c_priv)$/;"	f	file:
get_data	ast_mode.c	/^static int get_data(void *i2c_priv)$/;"	f	file:
get_ddr2_info	ast_post.c	/^static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)$/;"	f	file:
get_ddr3_info	ast_post.c	/^static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)$/;"	f	file:
get_fw_base	ast_dp501.c	/^static u32 get_fw_base(struct ast_private *ast)$/;"	f	file:
gr	ast_drv.h	/^	u8 gr[9];$/;"	m	struct:ast_vbios_stdtable
hde	ast_drv.h	/^	u32 hde;$/;"	m	struct:ast_vbios_enhtable
hdmitx_DISABLE_ACP_PKT	ast_hdmitx.h	684;"	d
hdmitx_DISABLE_AUD_INFOFRM_PKT	ast_hdmitx.h	688;"	d
hdmitx_DISABLE_AVI_INFOFRM_PKT	ast_hdmitx.h	687;"	d
hdmitx_DISABLE_GeneralPurpose_PKT	ast_hdmitx.h	691;"	d
hdmitx_DISABLE_ISRC1_PKT	ast_hdmitx.h	685;"	d
hdmitx_DISABLE_ISRC2_PKT	ast_hdmitx.h	686;"	d
hdmitx_DISABLE_MPG_INFOFRM_PKT	ast_hdmitx.h	690;"	d
hdmitx_DISABLE_NULL_PKT	ast_hdmitx.h	683;"	d
hdmitx_DISABLE_SPD_INFOFRM_PKT	ast_hdmitx.h	689;"	d
hdmitx_DISABLE_VSDB_PKT	ast_hdmitx.h	682;"	d
hdmitx_ENABLE_ACP_PKT	ast_hdmitx.h	674;"	d
hdmitx_ENABLE_AUD_INFOFRM_PKT	ast_hdmitx.h	678;"	d
hdmitx_ENABLE_AVI_INFOFRM_PKT	ast_hdmitx.h	677;"	d
hdmitx_ENABLE_GeneralPurpose_PKT	ast_hdmitx.h	681;"	d
hdmitx_ENABLE_ISRC1_PKT	ast_hdmitx.h	675;"	d
hdmitx_ENABLE_ISRC2_PKT	ast_hdmitx.h	676;"	d
hdmitx_ENABLE_MPG_INFOFRM_PKT	ast_hdmitx.h	680;"	d
hdmitx_ENABLE_NULL_PKT	ast_hdmitx.h	673;"	d
hdmitx_ENABLE_SPD_INFOFRM_PKT	ast_hdmitx.h	679;"	d
hdmitx_LoadRegSetting	ast_hdmitx.c	/^static void hdmitx_LoadRegSetting(struct drm_device *dev, RegSetEntry table[])$/;"	f	file:
hfp	ast_drv.h	/^	u32 hfp;$/;"	m	struct:ast_vbios_enhtable
hsync	ast_drv.h	/^	u32 hsync;$/;"	m	struct:ast_vbios_enhtable
ht	ast_drv.h	/^	u32 ht;$/;"	m	struct:ast_vbios_enhtable
i2c	ast_drv.h	/^	struct ast_i2c_chan *i2c;$/;"	m	struct:ast_connector	typeref:struct:ast_connector::ast_i2c_chan
index	ast_dram_tables.h	/^	u16 index;$/;"	m	struct:ast_dramstruct
invAndMask	ast_hdmitx.h	/^    u8 invAndMask ;$/;"	m	struct:structRegSetEntry
ioregs	ast_drv.h	/^	void __iomem *ioregs;$/;"	m	struct:ast_private
madj_max	ast_post.c	/^	u32 madj_max;$/;"	m	struct:ast2300_dram_param	file:
mclk	ast_drv.h	/^	uint32_t mclk;$/;"	m	struct:ast_private
misc	ast_drv.h	/^	u8 misc;$/;"	m	struct:ast_vbios_stdtable
mmc_test	ast_post.c	/^static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)$/;"	f	file:
mmc_test2	ast_post.c	/^static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)$/;"	f	file:
mmc_test_burst	ast_post.c	/^static bool mmc_test_burst(struct ast_private *ast, u32 datagen)$/;"	f	file:
mmc_test_burst2	ast_post.c	/^static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)$/;"	f	file:
mmc_test_single	ast_post.c	/^static bool mmc_test_single(struct ast_private *ast, u32 datagen)$/;"	f	file:
mmc_test_single2	ast_post.c	/^static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)$/;"	f	file:
mmc_test_single_2500	ast_post.c	/^static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen)$/;"	f	file:
mmctestburst2_ast2150	ast_post.c	/^static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)$/;"	f	file:
mode_id	ast_drv.h	/^	u32 mode_id;$/;"	m	struct:ast_vbios_enhtable
next_index	ast_drv.h	/^		unsigned int next_index;$/;"	m	struct:ast_private::__anon1
odt	ast_post.c	/^	u32 odt;$/;"	m	struct:ast2300_dram_param	file:
offset	ast_hdmitx.h	/^    u8 offset ;$/;"	m	struct:structRegSetEntry
offset_x	ast_drv.h	/^	u8 offset_x, offset_y;$/;"	m	struct:ast_crtc
offset_y	ast_drv.h	/^	u8 offset_x, offset_y;$/;"	m	struct:ast_crtc
param1	ast_drv.h	/^	u8 param1;$/;"	m	struct:ast_vbios_dclk_info
param2	ast_drv.h	/^	u8 param2;$/;"	m	struct:ast_vbios_dclk_info
param3	ast_drv.h	/^	u8 param3;$/;"	m	struct:ast_vbios_dclk_info
patch_ahb_ast2500	ast_post.c	/^void patch_ahb_ast2500(struct ast_private *ast)$/;"	f
pattern	ast_post.c	/^static const u32 pattern[8] = {$/;"	v	file:
pattern_AST2150	ast_post.c	/^static const u32 pattern_AST2150[14] = {$/;"	v	file:
pciidlist	ast_drv.c	/^static const struct pci_device_id pciidlist[] = {$/;"	v	typeref:struct:pci_device_id	file:
primary_plane	ast_drv.h	/^	struct drm_plane primary_plane;$/;"	m	struct:ast_private	typeref:struct:ast_private::drm_plane
refresh_rate	ast_drv.h	/^	u32 refresh_rate;$/;"	m	struct:ast_vbios_enhtable
refresh_rate_index	ast_drv.h	/^	u32 refresh_rate_index;$/;"	m	struct:ast_vbios_enhtable
reg_AC1	ast_post.c	/^	u32 reg_AC1;$/;"	m	struct:ast2300_dram_param	file:
reg_AC2	ast_post.c	/^	u32 reg_AC2;$/;"	m	struct:ast2300_dram_param	file:
reg_DQIDLY	ast_post.c	/^	u32 reg_DQIDLY;$/;"	m	struct:ast2300_dram_param	file:
reg_DQSIC	ast_post.c	/^	u32 reg_DQSIC;$/;"	m	struct:ast2300_dram_param	file:
reg_DRV	ast_post.c	/^	u32 reg_DRV;$/;"	m	struct:ast2300_dram_param	file:
reg_EMRS	ast_post.c	/^	u32 reg_EMRS;$/;"	m	struct:ast2300_dram_param	file:
reg_FREQ	ast_post.c	/^	u32 reg_FREQ;$/;"	m	struct:ast2300_dram_param	file:
reg_IOZ	ast_post.c	/^	u32 reg_IOZ;$/;"	m	struct:ast2300_dram_param	file:
reg_MADJ	ast_post.c	/^	u32 reg_MADJ;$/;"	m	struct:ast2300_dram_param	file:
reg_MRS	ast_post.c	/^	u32 reg_MRS;$/;"	m	struct:ast2300_dram_param	file:
reg_PERIOD	ast_post.c	/^	u32 reg_PERIOD;$/;"	m	struct:ast2300_dram_param	file:
reg_SADJ	ast_post.c	/^	u32 reg_SADJ;$/;"	m	struct:ast2300_dram_param	file:
regs	ast_drv.h	/^	void __iomem *regs;$/;"	m	struct:ast_private
res_1024x768	ast_tables.h	/^static const struct ast_vbios_enhtable res_1024x768[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_1152x864	ast_tables.h	/^static const struct ast_vbios_enhtable res_1152x864[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_1280x1024	ast_tables.h	/^static const struct ast_vbios_enhtable res_1280x1024[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_1280x800	ast_tables.h	/^static const struct ast_vbios_enhtable res_1280x800[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_1360x768	ast_tables.h	/^static const struct ast_vbios_enhtable res_1360x768[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_1440x900	ast_tables.h	/^static const struct ast_vbios_enhtable res_1440x900[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_1600x1200	ast_tables.h	/^static const struct ast_vbios_enhtable res_1600x1200[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_1600x900	ast_tables.h	/^static const struct ast_vbios_enhtable res_1600x900[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_1680x1050	ast_tables.h	/^static const struct ast_vbios_enhtable res_1680x1050[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_1920x1080	ast_tables.h	/^static const struct ast_vbios_enhtable res_1920x1080[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_1920x1200	ast_tables.h	/^static const struct ast_vbios_enhtable res_1920x1200[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_640x480	ast_tables.h	/^static const struct ast_vbios_enhtable res_640x480[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
res_800x600	ast_tables.h	/^static const struct ast_vbios_enhtable res_800x600[] = {$/;"	v	typeref:struct:ast_vbios_enhtable
reservedbuffer	ast_drv.h	/^	void __iomem *reservedbuffer;$/;"	m	struct:ast_private
reset_mmc_2500	ast_post.c	/^static void reset_mmc_2500(struct ast_private *ast)$/;"	f	file:
rodt	ast_post.c	/^	u32 rodt;$/;"	m	struct:ast2300_dram_param	file:
send_ack	ast_dp501.c	/^static void send_ack(struct ast_private *ast)$/;"	f	file:
send_nack	ast_dp501.c	/^static void send_nack(struct ast_private *ast)$/;"	f	file:
seq	ast_drv.h	/^	u8 seq[4];$/;"	m	struct:ast_vbios_stdtable
set_clock	ast_mode.c	/^static void set_clock(void *i2c_priv, int clock)$/;"	f	file:
set_cmd_trigger	ast_dp501.c	/^static void set_cmd_trigger(struct ast_private *ast)$/;"	f	file:
set_data	ast_mode.c	/^static void set_data(void *i2c_priv, int data)$/;"	f	file:
set_mpll_2500	ast_post.c	/^static void set_mpll_2500(struct ast_private *ast)$/;"	f	file:
std_table	ast_drv.h	/^	const struct ast_vbios_stdtable *std_table;$/;"	m	struct:ast_vbios_mode_info	typeref:struct:ast_vbios_mode_info::ast_vbios_stdtable
structRegSetEntry	ast_hdmitx.h	/^typedef struct structRegSetEntry {$/;"	s
support_newvga_mode	ast_drv.h	/^	bool support_newvga_mode;$/;"	m	struct:ast_private
support_wide_screen	ast_drv.h	/^	bool support_wide_screen;$/;"	m	struct:ast_private
to_ast_connector	ast_drv.h	255;"	d
to_ast_crtc	ast_drv.h	254;"	d
to_ast_crtc_state	ast_drv.h	301;"	d
tx_chip_type	ast_drv.h	/^	enum ast_tx_chip tx_chip_type;$/;"	m	struct:ast_private	typeref:enum:ast_private::ast_tx_chip
vbios_mode_info	ast_drv.h	/^	struct ast_vbios_mode_info vbios_mode_info;$/;"	m	struct:ast_crtc_state	typeref:struct:ast_crtc_state::ast_vbios_mode_info
vbios_stdtable	ast_tables.h	/^static const struct ast_vbios_stdtable vbios_stdtable[] = {$/;"	v	typeref:struct:ast_vbios_stdtable
vde	ast_drv.h	/^	u32 vde;$/;"	m	struct:ast_vbios_enhtable
vfp	ast_drv.h	/^	u32 vfp;$/;"	m	struct:ast_vbios_enhtable
vga2_clone	ast_drv.h	/^	bool vga2_clone;$/;"	m	struct:ast_private
vram_size	ast_drv.h	/^	uint32_t vram_size;$/;"	m	struct:ast_private
vram_size	ast_post.c	/^	u32 vram_size;$/;"	m	struct:ast2300_dram_param	file:
vsync	ast_drv.h	/^	u32 vsync;$/;"	m	struct:ast_vbios_enhtable
vt	ast_drv.h	/^	u32 vt;$/;"	m	struct:ast_vbios_enhtable
wait_ack	ast_dp501.c	/^static bool wait_ack(struct ast_private *ast)$/;"	f	file:
wait_nack	ast_dp501.c	/^static bool wait_nack(struct ast_private *ast)$/;"	f	file:
wodt	ast_post.c	/^	u32 wodt;$/;"	m	struct:ast2300_dram_param	file:
